| /hal_xtensa-latest/src/hal/ |
| D | cache.c | 35 const unsigned short Xthal_dcache_linesize = XCHAL_DCACHE_LINESIZE;
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| D | mem_ecc_parity.S | 65 # define CACHE_LINESIZE_MIN XCHAL_DCACHE_LINESIZE
173 addi a3, a3, XCHAL_DCACHE_LINESIZE-1
182 addi a2, a2, XCHAL_DCACHE_LINESIZE // increment to next line
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| D | cache_asm.S | 62 movi a7, -XCHAL_DCACHE_LINESIZE // for rounding to cache line size
72 movi a7, XCHAL_DCACHE_SIZE/XCHAL_DCACHE_LINESIZE // a7 = number of lines in dcache
73 movi a3, XCHAL_DCACHE_SIZE-XCHAL_DCACHE_LINESIZE // way index
84 addi a3, a3, -XCHAL_DCACHE_LINESIZE
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| D | mpu.c | 80 #if XCHAL_DCACHE_LINESIZE
81 #define CACHE_REGION_THRESHOLD (32 * XCHAL_DCACHE_LINESIZE / XCHAL_MPU_ALIGN)
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| /hal_xtensa-latest/include/xtensa/ |
| D | cacheasm.h | 628 …cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loop…
679 cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
731 cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
825 cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
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| /hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/ |
| D | core-isa.h | 158 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/ |
| D | core-isa.h | 240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/ |
| D | core-isa.h | 240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/ |
| D | core-isa.h | 240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/ |
| D | core-isa.h | 240 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/ |
| D | core-isa.h | 233 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/ |
| D | core-isa.h | 213 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/ |
| D | core-isa.h | 213 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/ |
| D | core-isa.h | 292 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/ |
| D | core-isa.h | 292 #define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/ |
| D | core-isa.h | 285 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/ |
| D | core-isa.h | 238 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/ |
| D | core-isa.h | 280 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ macro
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| D | core.h | 675 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
680 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
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| /hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/ |
| D | core-isa.h | 292 #define XCHAL_DCACHE_LINESIZE 256 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/ |
| D | core-isa.h | 290 #define XCHAL_DCACHE_LINESIZE 8 /* D-cache line size in bytes */ macro
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| /hal_xtensa-latest/include/xtensa/config/ |
| D | core.h | 778 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
783 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE
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