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Searched refs:XSHAL_XT2000_CACHEATTR_BYPASS (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h139 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
200 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFFF22222 /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h139 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
200 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h145 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
206 #define XSHAL_XT2000_CACHEATTR_BYPASS 0x2F222F22 /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dsystem.h144 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
205 #define XSHAL_XT2000_CACHEATTR_BYPASS 0x33CCC33C /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h156 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
217 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFFF2222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h156 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
217 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h156 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
217 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFFF2222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ macro