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Searched refs:XSHAL_STRICT_CACHEATTR_WRITEALLOC (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h158 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFFFF11 /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h158 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF1111FF /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h164 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0x1F1FFFF1 /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dsystem.h163 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xBBCCCCCC /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h175 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFF1F1FF /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h175 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h175 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFFFF1F /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h179 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h179 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h179 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h179 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ macro