Home
last modified time | relevance | path

Searched refs:XSHAL_IOBLOCK_CACHED_SIZE (Results 1 – 11 of 11) sorted by relevance

/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h77 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h77 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h77 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dsystem.h80 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dsystem.h87 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h87 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h87 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h91 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h91 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h91 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h91 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 macro