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Searched refs:INTENABLE (Results 1 – 8 of 8) sorted by relevance

/hal_xtensa-2.7.6/zephyr/soc/nxp_imx8/xtensa/config/
Dspecreg.h71 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/sample_controller/xtensa/config/
Dspecreg.h71 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_apl_adsp/xtensa/config/
Dspecreg.h85 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_18/xtensa/config/
Dspecreg.h86 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_s1000/xtensa/config/
Dspecreg.h84 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_25/xtensa/config/
Dspecreg.h86 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/zephyr/soc/intel_cavs_20/xtensa/config/
Dspecreg.h86 #define INTENABLE 228 macro
/hal_xtensa-2.7.6/include/xtensa/
Dspecreg.h95 #define INTENABLE 228 macro