1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #if !defined __XCC__ 29 30 #ifndef XTENSA_SPECREG_H 31 #define XTENSA_SPECREG_H 32 33 /* Include these special register bitfield definitions, for historical reasons: */ 34 #include <xtensa/corebits.h> 35 36 37 /* Special registers: */ 38 #define LBEG 0 39 #define LEND 1 40 #define LCOUNT 2 41 #define SAR 3 42 #define BR 4 43 #define SCOMPARE1 12 44 #define PREFCTL 40 45 #define WINDOWBASE 72 46 #define WINDOWSTART 73 47 #define IBREAKENABLE 96 48 #define ATOMCTL 99 49 #define DDR 104 50 #define MEPC 106 51 #define MEPS 107 52 #define MESAVE 108 53 #define MESR 109 54 #define MECR 110 55 #define MEVADDR 111 56 #define IBREAKA_0 128 57 #define IBREAKA_1 129 58 #define DBREAKA_0 144 59 #define DBREAKA_1 145 60 #define DBREAKC_0 160 61 #define DBREAKC_1 161 62 #define EPC_1 177 63 #define EPC_2 178 64 #define EPC_3 179 65 #define EPC_4 180 66 #define EPC_5 181 67 #define EPC_6 182 68 #define EPC_7 183 69 #define DEPC 192 70 #define EPS_2 194 71 #define EPS_3 195 72 #define EPS_4 196 73 #define EPS_5 197 74 #define EPS_6 198 75 #define EPS_7 199 76 #define EXCSAVE_1 209 77 #define EXCSAVE_2 210 78 #define EXCSAVE_3 211 79 #define EXCSAVE_4 212 80 #define EXCSAVE_5 213 81 #define EXCSAVE_6 214 82 #define EXCSAVE_7 215 83 #define CPENABLE 224 84 #define INTERRUPT 226 85 #define INTENABLE 228 86 #define PS 230 87 #define VECBASE 231 88 #define EXCCAUSE 232 89 #define DEBUGCAUSE 233 90 #define CCOUNT 234 91 #define PRID 235 92 #define ICOUNT 236 93 #define ICOUNTLEVEL 237 94 #define EXCVADDR 238 95 #define CCOMPARE_0 240 96 #define CCOMPARE_1 241 97 #define CCOMPARE_2 242 98 99 /* Special cases (bases of special register series): */ 100 #define IBREAKA 128 101 #define DBREAKA 144 102 #define DBREAKC 160 103 #define EPC 176 104 #define EPS 192 105 #define EXCSAVE 208 106 #define CCOMPARE 240 107 108 #endif /* XTENSA_SPECREG_H */ 109 110 #else 111 112 #error "xcc should not use this header" 113 114 #endif /* __XCC__ */ 115
