1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Customer ID=12445; Build=0x700c0; Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define BR 4 41 #define SCOMPARE1 12 42 #define PREFCTL 40 43 #define WINDOWBASE 72 44 #define WINDOWSTART 73 45 #define IBREAKENABLE 96 46 #define ATOMCTL 99 47 #define DDR 104 48 #define IBREAKA_0 128 49 #define IBREAKA_1 129 50 #define DBREAKA_0 144 51 #define DBREAKA_1 145 52 #define DBREAKC_0 160 53 #define DBREAKC_1 161 54 #define EPC_1 177 55 #define EPC_2 178 56 #define EPC_3 179 57 #define EPC_4 180 58 #define EPC_5 181 59 #define DEPC 192 60 #define EPS_2 194 61 #define EPS_3 195 62 #define EPS_4 196 63 #define EPS_5 197 64 #define EXCSAVE_1 209 65 #define EXCSAVE_2 210 66 #define EXCSAVE_3 211 67 #define EXCSAVE_4 212 68 #define EXCSAVE_5 213 69 #define CPENABLE 224 70 #define INTERRUPT 226 71 #define INTENABLE 228 72 #define PS 230 73 #define VECBASE 231 74 #define EXCCAUSE 232 75 #define DEBUGCAUSE 233 76 #define CCOUNT 234 77 #define PRID 235 78 #define ICOUNT 236 79 #define ICOUNTLEVEL 237 80 #define EXCVADDR 238 81 #define CCOMPARE_0 240 82 #define CCOMPARE_1 241 83 #define MISC_REG_0 244 84 #define MISC_REG_1 245 85 86 /* Special cases (bases of special register series): */ 87 #define IBREAKA 128 88 #define DBREAKA 144 89 #define DBREAKC 160 90 #define EPC 176 91 #define EPS 192 92 #define EXCSAVE 208 93 #define CCOMPARE 240 94 95 /* Special names for read-only and write-only interrupt registers: */ 96 #define INTREAD 226 97 #define INTSET 226 98 #define INTCLEAR 227 99 100 #endif /* XTENSA_SPECREG_H */ 101 102
