Searched refs:REG_ADDR8 (Results 1 – 21 of 21) sorted by relevance
33 #define reg_gpio_pa_in REG_ADDR8(0x140300)34 #define reg_gpio_pa_ie REG_ADDR8(0x140301)35 #define reg_gpio_pa_oen REG_ADDR8(0x140302)36 #define reg_gpio_pa_out REG_ADDR8(0x140303)39 #define reg_gpio_pa_pol REG_ADDR8(0x140304)40 #define reg_gpio_pa_ds REG_ADDR8(0x140305)41 #define reg_gpio_pa_gpio REG_ADDR8(0x140306)42 #define reg_gpio_pa_irq_en REG_ADDR8(0x140307)45 #define reg_gpio_pa_fuc_l REG_ADDR8(0x140330)46 #define reg_gpio_pa_fuc_h REG_ADDR8(0x140331)[all …]
32 #define reg_ctrl_ep_ptr REG_ADDR8(0x100800)33 #define reg_ctrl_ep_dat REG_ADDR8(0x100801)34 #define reg_ctrl_ep_ctrl REG_ADDR8(0x100802)42 #define reg_ctrl_ep_irq_sta REG_ADDR8(0x100803)51 #define reg_ctrl_ep_irq_mode REG_ADDR8(0x100804)63 #define reg_usb_ctrl REG_ADDR8(0x100805)73 #define reg_usb_mdev REG_ADDR8(0x10080a)82 #define reg_usb_host_conn REG_ADDR8(0x10080b)83 #define reg_usb_sups_cyc_cali REG_ADDR8(0x10080c)84 #define reg_usb_intf_alt REG_ADDR8(0x10080d)[all …]
44 #define reg_rf_bb_auto_ctrl REG_ADDR8(0x10050c)54 #define reg_rf_bb_tx_chn_dep REG_ADDR8(0x1004f3)55 #define reg_rf_bb_tx_size REG_ADDR8(0x1004f2)57 #define reg_rf_dma_rx_wptr REG_ADDR8(0x001004f4)58 #define reg_rf_dma_rx_rptr REG_ADDR8(0x001004f5)60 #define reg_rf_dma_tx_rptr(i) REG_ADDR8(0x00100501 + (i << 1))61 #define reg_rf_dma_tx_wptr(i) REG_ADDR8(0x00100500 + (i << 1))63 #define reg_rf_bb_rx_size REG_ADDR8(CHNADDR+0xf6)67 #define reg_rf_rx_wptr_mask REG_ADDR8(CHNADDR+0x10d)75 #define reg_rf_tx_mode1 REG_ADDR8(REG_BASEBAND_BASE_ADDR)[all …]
56 #define reg_spi_mode0(i) REG_ADDR8(PSPI_BASE_ADDR+(i)*BASE_ADDR_DIFF)71 #define reg_spi_mode1(i) REG_ADDR8(PSPI_BASE_ADDR+0x01+(i)*BASE_ADDR_DIFF)79 #define reg_spi_mode2(i) REG_ADDR8(PSPI_BASE_ADDR+0x02+(i)*BASE_ADDR_DIFF)93 #define reg_spi_tx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x03+(i)*BASE_ADDR_DIFF)99 #define reg_spi_tx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x12+(i)*(BASE_ADDR_DIFF-0x12+0x20))105 #define reg_spi_tx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x13+(i)*(BASE_ADDR_DIFF-0x13+0x21))110 #define reg_spi_rx_cnt0(i) REG_ADDR8(PSPI_BASE_ADDR+0x04+(i)*BASE_ADDR_DIFF)116 #define reg_spi_rx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR+0x10+(i)*(BASE_ADDR_DIFF-0x10+0x1e))121 #define reg_spi_rx_cnt2(i) REG_ADDR8(PSPI_BASE_ADDR+0x11+(i)*(BASE_ADDR_DIFF-0x11+0x1f))141 #define reg_spi_trans0(i) REG_ADDR8(PSPI_BASE_ADDR+0x05+(i)*BASE_ADDR_DIFF)[all …]
35 #define reg_audio_en REG_ADDR8(REG_AUDIO_APB_BASE+0x00)44 #define reg_i2s_cfg REG_ADDR8(REG_AUDIO_APB_BASE+0x01)55 #define reg_i2s_cfg2 REG_ADDR8(REG_AUDIO_APB_BASE+0x02)61 #define reg_audio_ctrl REG_ADDR8(REG_AUDIO_APB_BASE+0x03)69 #define reg_audio_tune REG_ADDR8(REG_AUDIO_APB_BASE+0x04)78 #define reg_audio_sel REG_ADDR8(REG_AUDIO_APB_BASE+0x05)87 #define reg_audio_i2c_addr REG_ADDR8(REG_AUDIO_APB_BASE+0x08)88 #define reg_audio_i2c_mode REG_ADDR8(REG_AUDIO_APB_BASE+0x09)90 #define reg_fifo_trig0 REG_ADDR8(REG_AUDIO_APB_BASE+0x0a)92 #define reg_audio_ptr_set REG_ADDR8(REG_AUDIO_APB_BASE+0x10)[all …]
45 #define reg_i2c_sp REG_ADDR8(REG_I2C_BASE)53 #define reg_i2c_id REG_ADDR8(REG_I2C_BASE+0x01)68 #define reg_i2c_mst REG_ADDR8(REG_I2C_BASE+0x02)92 #define reg_i2c_sct0 REG_ADDR8(REG_I2C_BASE+0x03)119 #define reg_i2c_sct1 REG_ADDR8(REG_I2C_BASE+0x04)137 #define reg_i2c_trig REG_ADDR8(REG_I2C_BASE+0x05)145 #define reg_i2c_len REG_ADDR8(REG_I2C_BASE+0x06)156 #define reg_i2c_slave_strech_en REG_ADDR8(REG_I2C_BASE+0x07)165 #define reg_i2c_data_buf(i) REG_ADDR8(( REG_I2C_BASE+0x08 +(i) ))170 #define reg_i2c_data_buf0 REG_ADDR8(REG_I2C_BASE+0x08)[all …]
32 #define reg_mspi_data REG_ADDR8(0x140100)34 #define reg_mspi_fm REG_ADDR8(0x140101)42 #define reg_mspi_status REG_ADDR8(0x140102)47 #define reg_mspi_fm1 REG_ADDR8(0x140103)55 #define reg_mspi_set_l REG_ADDR8(0x140104)60 #define reg_mspi_set_h REG_ADDR8(0x140105)65 #define reg_mspi_cmd_ahb REG_ADDR8(0x140106)70 #define reg_mspi_fm_ahb REG_ADDR8(0x140107)
47 #define reg_pwm_enable REG_ADDR8(REG_PWM_BASE)60 #define reg_pwm0_enable REG_ADDR8(REG_PWM_BASE+0x01)69 #define reg_pwm_clkdiv REG_ADDR8(REG_PWM_BASE+0x02)75 #define reg_pwm0_mode REG_ADDR8(REG_PWM_BASE+0x03)82 #define reg_pwm_invert REG_ADDR8(REG_PWM_BASE+0x04)97 #define reg_pwm_n_invert REG_ADDR8(REG_PWM_BASE+0x05)118 #define reg_pwm_pol REG_ADDR8(REG_PWM_BASE+0x06)134 #define reg_pwm_mode32k REG_ADDR8(REG_PWM_BASE+0x07)173 #define reg_pwm_cnt5_l REG_ADDR8(REG_PWM_BASE+0x3e)182 #define reg_pwm0_pulse_num0 REG_ADDR8(REG_PWM_BASE+0x2c)//0x2c[7:0][all …]
42 #define reg_rst0 REG_ADDR8(0x1401e0)55 #define reg_rst1 REG_ADDR8(0x1401e1)67 #define reg_rst2 REG_ADDR8(0x1401e2)79 #define reg_rst3 REG_ADDR8(0x1401e3)93 #define reg_clk_en0 REG_ADDR8(0x1401e4)104 #define reg_clk_en1 REG_ADDR8(0x1401e5)115 #define reg_clk_en2 REG_ADDR8(0x1401e6)126 #define reg_clk_en3 REG_ADDR8(0x1401e7)133 #define reg_clk_sel0 REG_ADDR8(0x1401e8)140 #define reg_clk_sel1 REG_ADDR8(0x1401e9)[all …]
32 #define reg_ana_addr REG_ADDR8(ALG_BASE_ADDR)33 #define reg_ana_ctrl REG_ADDR8(ALG_BASE_ADDR+0x02)45 #define reg_ana_len REG_ADDR8(ALG_BASE_ADDR+0x03)46 #define reg_ana_data(n) REG_ADDR8(ALG_BASE_ADDR+0x04+(n))50 #define reg_ana_sta REG_ADDR8(ALG_BASE_ADDR+0x09)55 #define reg_ana_irq_sta REG_ADDR8(ALG_BASE_ADDR+0x0a)61 #define reg_ana_dma_ctl REG_ADDR8(ALG_BASE_ADDR+0x0b)
32 #define reg_tmr_ctrl0 REG_ADDR8(0x140140)44 #define reg_tmr_ctrl2 REG_ADDR8(0x140142)50 #define reg_tmr_sta REG_ADDR8(0x140143)63 #define reg_wt_target0 REG_ADDR8(0x14014c)// always is 0x0064 #define reg_wt_target1 REG_ADDR8(0x14014d)65 #define reg_wt_target2 REG_ADDR8(0x14014e)66 #define reg_wt_target3 REG_ADDR8(0x14014f)
35 #define reg_uart_data_buf(i,j) REG_ADDR8(reg_uart_data_buf_adr(i)+(j)) //uart(i)_buf(j)47 #define reg_uart_ctrl0(i) REG_ADDR8(0x140086+(i)*0x40)55 #define reg_uart_ctrl1(i) REG_ADDR8(0x140087+(i)*0x40)78 #define reg_uart_ctrl3(i) REG_ADDR8(0x140089+(i)*0x40)85 #define reg_uart_rx_timeout0(i) REG_ADDR8(0x14008a+(i)*0x40)91 #define reg_uart_rx_timeout1(i) REG_ADDR8(0x14008b+0x40*(i))104 #define reg_uart_buf_cnt(i) REG_ADDR8(0x14008c+(i)*0x40)110 #define reg_uart_status1(i) REG_ADDR8(0x14008d+((i)*0x40))121 #define reg_uart_status2(i) REG_ADDR8((0x14008e) +(0x40*(i)))130 #define reg_uart_state(i) REG_ADDR8(0x14008f+0x40*(i))[all …]
64 #define reg_dma_ctr0(i) REG_ADDR8(( 0x00100444 +(i)*0x14))67 #define reg_dma_err_isr REG_ADDR8(0x100430)68 #define reg_dma_abt_isr REG_ADDR8(0x100431)69 #define reg_dma_tc_isr REG_ADDR8(0x100432)86 #define reg_dma_ctr3(i) REG_ADDR8((0x00100447 +(i)*0x14))119 #define reg_dma_rx_wptr REG_ADDR8(0x801004f4)120 #define reg_dma_tx_wptr REG_ADDR8(0x80100500)127 #define reg_dma_rx_rptr REG_ADDR8(0x801004f5)128 #define reg_dma_tx_rptr REG_ADDR8(0x80100501)
37 #define reg_swire_data REG_ADDR8(SWIRE_BASE_ADDR)39 #define reg_swire_ctl REG_ADDR8(SWIRE_BASE_ADDR+1)51 #define reg_swire_ctl2 REG_ADDR8(SWIRE_BASE_ADDR+2)56 #define reg_swire_id REG_ADDR8(SWIRE_BASE_ADDR+3)
37 #define reg_system_irq_mask REG_ADDR8(STIMER_BASE_ADDR+0x8)43 #define reg_system_cal_irq REG_ADDR8(STIMER_BASE_ADDR+0x9)50 #define reg_system_ctrl REG_ADDR8(STIMER_BASE_ADDR+0xa)60 #define reg_system_st REG_ADDR8(STIMER_BASE_ADDR+0xb)
34 #define reg_trng_cr0 REG_ADDR8(REG_TRNG_BASE)48 #define reg_rbg_sr REG_ADDR8(REG_TRNG_BASE+0x08)
56 p[0] = REG_ADDR8(0x140300); in gpio_read_all()57 p[1] = REG_ADDR8(0x140308); in gpio_read_all()58 p[2] = REG_ADDR8(0x140310); in gpio_read_all()59 p[3] = REG_ADDR8(0x140318); in gpio_read_all()60 p[4] = REG_ADDR8(0x140320); in gpio_read_all()
79 REG_ADDR8(0x801404e3) = 0; //rf_reset_baseband,rf reg need re-setting in rf_reset_baseband()80 REG_ADDR8(0x801404e3) = BIT(0); //release reset signal in rf_reset_baseband()111 REG_ADDR8(0x80140a01) = 0x01; in reset_sn_nesn()219 #define STOP_RF_STATE_MACHINE ( REG_ADDR8(0x80140a00) = 0x80 )
343 #define reg_usb_irq REG_ADDR8(0x100839)
110 REG_ADDR8(0x140218) = 0x02; //sys tick 16M set upon next 32k posedge in pm_stimer_recover()124 REG_ADDR8(0x140218) = 0;//normal sys tick (16/sys) update in pm_stimer_recover()461 …REG_ADDR8(0x140218) = 0x01; //system tick only update upon 32k posedge, must set before enable 32… in pm_sleep_wakeup()617 REG_ADDR8(0x140218) = 0x02; //sys tick 16M set upon next 32k posedge in pm_sleep_wakeup()632 REG_ADDR8(0x140218) = 0; //normal sys tick (16/sys) update in pm_sleep_wakeup()
70 #define REG_ADDR8(a) (*(volatile unsigned char*)(REG_RW_BASE_ADDR | (a))) macro
