1 /******************************************************************************
2  * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3  * All rights reserved.
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  *   http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  *****************************************************************************/
18 
19 /********************************************************************************************************
20  * @file	trng_reg.h
21  *
22  * @brief	This is the header file for B91
23  *
24  * @author	Driver Group
25  *
26  *******************************************************************************************************/
27 #ifndef TRNG_REG_H_
28 #define TRNG_REG_H_
29 
30 /*******************************      trng registers: 101800      ******************************/
31 #define REG_TRNG_BASE					0x101800
32 
33 
34 #define reg_trng_cr0					REG_ADDR8(REG_TRNG_BASE)
35 enum{
36 	FLD_TRNG_CR0_RBGEN		= 	BIT(0),
37 	FLD_TRNG_CR0_ROSEN0 	= 	BIT(1),
38 	FLD_TRNG_CR0_ROSEN1 	= 	BIT(2),
39 	FLD_TRNG_CR0_ROSEN2 	= 	BIT(3),
40 	FLD_TRNG_CR0_ROSEN3 	= 	BIT(4),
41 };
42 
43 #define reg_trng_rtcr					REG_ADDR32(REG_TRNG_BASE+0x04)
44 enum{
45 	FLD_TRNG_RTCR_MSEL		= 	BIT(0),
46 };
47 
48 #define reg_rbg_sr						REG_ADDR8(REG_TRNG_BASE+0x08)
49 enum{
50 	FLD_RBG_SR_DRDY			= 	BIT(0),
51 };
52 
53 #define reg_rbg_dr						REG_ADDR32(REG_TRNG_BASE+0x0c)
54 
55 #endif
56