Lines Matching refs:REG_ADDR8
42 #define reg_rst0 REG_ADDR8(0x1401e0)
55 #define reg_rst1 REG_ADDR8(0x1401e1)
67 #define reg_rst2 REG_ADDR8(0x1401e2)
79 #define reg_rst3 REG_ADDR8(0x1401e3)
93 #define reg_clk_en0 REG_ADDR8(0x1401e4)
104 #define reg_clk_en1 REG_ADDR8(0x1401e5)
115 #define reg_clk_en2 REG_ADDR8(0x1401e6)
126 #define reg_clk_en3 REG_ADDR8(0x1401e7)
133 #define reg_clk_sel0 REG_ADDR8(0x1401e8)
140 #define reg_clk_sel1 REG_ADDR8(0x1401e9)
145 #define reg_i2s_step REG_ADDR8(SC_BASE_ADDR+0x2a)
151 #define reg_i2s_mod REG_ADDR8(SC_BASE_ADDR+0x2b)
154 #define reg_dmic_step REG_ADDR8(SC_BASE_ADDR+0x2c)
160 #define reg_dmic_mod REG_ADDR8(SC_BASE_ADDR+0x2d)
162 #define reg_wakeup_en REG_ADDR8(SC_BASE_ADDR+0x2e)
170 #define reg_dmic_clk_set REG_ADDR8(SC_BASE_ADDR+0x33)