Home
last modified time | relevance | path

Searched refs:XSPI_WPCCR_ISIZE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11061 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
11062 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11064 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11065 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11473 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32h562xx.h11787 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
11788 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11790 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11791 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
12199 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32h533xx.h11470 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
11471 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11473 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11474 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
11882 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32h573xx.h14280 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
14281 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
14283 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
14284 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
14692 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32h563xx.h13871 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13872 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
13874 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
13875 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x000…
14283 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12153 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
12154 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12156 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12157 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12572 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u535xx.h11753 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
11754 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
11756 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
11757 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12172 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u595xx.h13103 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13104 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13106 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13107 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13556 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
13967 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5a5xx.h13552 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13553 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13555 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13556 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
14005 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
14416 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5f7xx.h14601 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
14602 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
14604 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
14605 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
15054 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
15465 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u575xx.h12788 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
12789 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12791 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
12792 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13207 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u599xx.h16822 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
16823 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
16825 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
16826 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17275 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
17686 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5g7xx.h15050 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
15051 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
15053 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
15054 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
15503 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
15914 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5f9xx.h17727 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
17728 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17730 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17731 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
18180 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
18591 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5a9xx.h17271 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
17272 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17274 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17275 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
17724 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
18135 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u5g9xx.h18176 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
18177 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
18179 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
18180 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
18629 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
19040 #define HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
Dstm32u585xx.h13237 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13238 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13240 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13241 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00…
13656 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13396 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13397 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
13399 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
13400 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7s7xx.h14430 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
14431 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
14433 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
14434 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7s3xx.h14028 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
14029 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
14031 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
14032 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7r7xx.h13796 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
13797 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
13799 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
13800 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39434 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
39435 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
39437 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
39438 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32n657xx.h41073 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
41074 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
41076 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
41077 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32n655xx.h40684 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
40685 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
40687 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
40688 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32n647xx.h39823 #define XSPI_WPCCR_ISIZE_Pos (4U) macro
39824 #define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
39826 #define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
39827 #define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */