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Searched refs:XSPI_WPCCR_IMODE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11052 #define XSPI_WPCCR_IMODE_Pos (0U) macro
11053 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11055 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11056 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11057 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11464 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32h562xx.h11778 #define XSPI_WPCCR_IMODE_Pos (0U) macro
11779 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11781 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11782 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11783 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
12190 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32h533xx.h11461 #define XSPI_WPCCR_IMODE_Pos (0U) macro
11462 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11464 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11465 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11466 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
11873 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32h573xx.h14271 #define XSPI_WPCCR_IMODE_Pos (0U) macro
14272 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
14274 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
14275 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
14276 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
14683 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32h563xx.h13862 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13863 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
13865 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
13866 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
13867 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x000…
14274 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12144 #define XSPI_WPCCR_IMODE_Pos (0U) macro
12145 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12147 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12148 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12149 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12563 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u535xx.h11744 #define XSPI_WPCCR_IMODE_Pos (0U) macro
11745 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
11747 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
11748 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
11749 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12163 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u595xx.h13094 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13095 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13097 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13098 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13099 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13547 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
13958 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5a5xx.h13543 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13544 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13546 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13547 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13548 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13996 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
14407 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5f7xx.h14592 #define XSPI_WPCCR_IMODE_Pos (0U) macro
14593 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
14595 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
14596 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
14597 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
15045 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
15456 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u575xx.h12779 #define XSPI_WPCCR_IMODE_Pos (0U) macro
12780 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12782 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12783 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
12784 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13198 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u599xx.h16813 #define XSPI_WPCCR_IMODE_Pos (0U) macro
16814 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
16816 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
16817 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
16818 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17266 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
17677 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5g7xx.h15041 #define XSPI_WPCCR_IMODE_Pos (0U) macro
15042 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
15044 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
15045 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
15046 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
15494 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
15905 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u585xx.h13228 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13229 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13231 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13232 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13233 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
13647 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5f9xx.h17718 #define XSPI_WPCCR_IMODE_Pos (0U) macro
17719 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17721 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17722 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17723 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
18171 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
18582 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5a9xx.h17262 #define XSPI_WPCCR_IMODE_Pos (0U) macro
17263 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17265 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17266 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17267 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
17715 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
18126 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
Dstm32u5g9xx.h18167 #define XSPI_WPCCR_IMODE_Pos (0U) macro
18168 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
18170 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
18171 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
18172 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00…
18620 #define OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
19031 #define HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13387 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13388 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
13390 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
13391 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
13392 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7s7xx.h14421 #define XSPI_WPCCR_IMODE_Pos (0U) macro
14422 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
14424 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
14425 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
14426 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7s3xx.h14019 #define XSPI_WPCCR_IMODE_Pos (0U) macro
14020 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
14022 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
14023 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
14024 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7r7xx.h13787 #define XSPI_WPCCR_IMODE_Pos (0U) macro
13788 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
13790 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
13791 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
13792 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39425 #define XSPI_WPCCR_IMODE_Pos (0U) macro
39426 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
39428 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
39429 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
39430 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n657xx.h41064 #define XSPI_WPCCR_IMODE_Pos (0U) macro
41065 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
41067 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
41068 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
41069 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n655xx.h40675 #define XSPI_WPCCR_IMODE_Pos (0U) macro
40676 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
40678 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
40679 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
40680 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n647xx.h39814 #define XSPI_WPCCR_IMODE_Pos (0U) macro
39815 #define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
39817 #define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
39818 #define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
39819 #define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */