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Searched refs:XSPI_WPCCR_DDTR_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13142 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13143 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
13595 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
14006 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5a5xx.h13591 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13592 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
14044 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
14455 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5f7xx.h14640 #define XSPI_WPCCR_DDTR_Pos (27U) macro
14641 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
15093 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
15504 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u545xx.h12192 #define XSPI_WPCCR_DDTR_Pos (27U) macro
12193 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
12611 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u535xx.h11792 #define XSPI_WPCCR_DDTR_Pos (27U) macro
11793 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
12211 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u599xx.h16861 #define XSPI_WPCCR_DDTR_Pos (27U) macro
16862 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
17314 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
17725 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5g7xx.h15089 #define XSPI_WPCCR_DDTR_Pos (27U) macro
15090 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
15542 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
15953 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5f9xx.h17766 #define XSPI_WPCCR_DDTR_Pos (27U) macro
17767 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
18219 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
18630 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5a9xx.h17310 #define XSPI_WPCCR_DDTR_Pos (27U) macro
17311 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
17763 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
18174 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u5g9xx.h18215 #define XSPI_WPCCR_DDTR_Pos (27U) macro
18216 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
18668 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
19079 #define HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u575xx.h12827 #define XSPI_WPCCR_DDTR_Pos (27U) macro
12828 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
13246 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32u585xx.h13276 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13277 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08…
13695 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11100 #define XSPI_WPCCR_DDTR_Pos (27U) macro
11101 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x080…
11512 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32h562xx.h11826 #define XSPI_WPCCR_DDTR_Pos (27U) macro
11827 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x080…
12238 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32h533xx.h11509 #define XSPI_WPCCR_DDTR_Pos (27U) macro
11510 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x080…
11921 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32h573xx.h14319 #define XSPI_WPCCR_DDTR_Pos (27U) macro
14320 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x080…
14731 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
Dstm32h563xx.h13910 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13911 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x080…
14322 #define OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13435 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13436 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s7xx.h14469 #define XSPI_WPCCR_DDTR_Pos (27U) macro
14470 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s3xx.h14067 #define XSPI_WPCCR_DDTR_Pos (27U) macro
14068 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7r7xx.h13835 #define XSPI_WPCCR_DDTR_Pos (27U) macro
13836 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39473 #define XSPI_WPCCR_DDTR_Pos (27U) macro
39474 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n657xx.h41112 #define XSPI_WPCCR_DDTR_Pos (27U) macro
41113 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n655xx.h40723 #define XSPI_WPCCR_DDTR_Pos (27U) macro
40724 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n647xx.h39862 #define XSPI_WPCCR_DDTR_Pos (27U) macro
39863 #define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */