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Searched refs:XSPI_WPCCR_ABSIZE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11089 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
11090 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x003…
11092 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x001…
11093 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x002…
11501 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32h562xx.h11815 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
11816 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x003…
11818 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x001…
11819 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x002…
12227 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32h533xx.h11498 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
11499 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x003…
11501 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x001…
11502 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x002…
11910 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32h573xx.h14308 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
14309 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x003…
14311 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x001…
14312 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x002…
14720 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32h563xx.h13899 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13900 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x003…
13902 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x001…
13903 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x002…
14311 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12181 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
12182 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12184 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12185 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12600 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u535xx.h11781 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
11782 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
11784 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
11785 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12200 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u595xx.h13131 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13132 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13134 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13135 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13584 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
13995 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5a5xx.h13580 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13581 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13583 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13584 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
14033 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
14444 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5f7xx.h14629 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
14630 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
14632 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
14633 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
15082 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
15493 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u575xx.h12816 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
12817 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12819 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
12820 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13235 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u599xx.h16850 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
16851 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
16853 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
16854 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17303 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
17714 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5g7xx.h15078 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
15079 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
15081 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
15082 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
15531 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
15942 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5f9xx.h17755 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
17756 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17758 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17759 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
18208 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
18619 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5a9xx.h17299 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
17300 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17302 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17303 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
17752 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
18163 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u5g9xx.h18204 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
18205 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
18207 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
18208 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
18657 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
19068 #define HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
Dstm32u585xx.h13265 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13266 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13268 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13269 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00…
13684 #define OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13424 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13425 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
13427 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
13428 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32h7s7xx.h14458 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
14459 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
14461 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
14462 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32h7s3xx.h14056 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
14057 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
14059 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
14060 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32h7r7xx.h13824 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
13825 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
13827 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
13828 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39462 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
39463 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
39465 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
39466 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32n657xx.h41101 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
41102 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
41104 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
41105 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32n655xx.h40712 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
40713 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
40715 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
40716 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
Dstm32n647xx.h39851 #define XSPI_WPCCR_ABSIZE_Pos (20U) macro
39852 #define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
39854 #define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
39855 #define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */