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Searched refs:XSPI_WCCR_IMODE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11129 #define XSPI_WCCR_IMODE_Pos (0U) macro
11130 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11132 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11133 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11134 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11541 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32h562xx.h11855 #define XSPI_WCCR_IMODE_Pos (0U) macro
11856 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11858 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11859 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11860 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
12267 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32h533xx.h11538 #define XSPI_WCCR_IMODE_Pos (0U) macro
11539 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11541 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11542 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11543 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
11950 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32h573xx.h14348 #define XSPI_WCCR_IMODE_Pos (0U) macro
14349 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
14351 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
14352 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
14353 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
14760 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32h563xx.h13939 #define XSPI_WCCR_IMODE_Pos (0U) macro
13940 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
13942 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
13943 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
13944 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x000…
14351 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12221 #define XSPI_WCCR_IMODE_Pos (0U) macro
12222 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12224 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12225 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12226 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12640 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u535xx.h11821 #define XSPI_WCCR_IMODE_Pos (0U) macro
11822 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
11824 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
11825 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
11826 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12240 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u595xx.h13171 #define XSPI_WCCR_IMODE_Pos (0U) macro
13172 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13174 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13175 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13176 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13624 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
14035 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5a5xx.h13620 #define XSPI_WCCR_IMODE_Pos (0U) macro
13621 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13623 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13624 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13625 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
14073 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
14484 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5f7xx.h14669 #define XSPI_WCCR_IMODE_Pos (0U) macro
14670 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
14672 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
14673 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
14674 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
15122 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
15533 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u575xx.h12856 #define XSPI_WCCR_IMODE_Pos (0U) macro
12857 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12859 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12860 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
12861 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13275 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u599xx.h16890 #define XSPI_WCCR_IMODE_Pos (0U) macro
16891 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
16893 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
16894 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
16895 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17343 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
17754 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5g7xx.h15118 #define XSPI_WCCR_IMODE_Pos (0U) macro
15119 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
15121 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
15122 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
15123 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
15571 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
15982 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u585xx.h13305 #define XSPI_WCCR_IMODE_Pos (0U) macro
13306 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13308 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13309 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13310 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
13724 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5f9xx.h17795 #define XSPI_WCCR_IMODE_Pos (0U) macro
17796 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17798 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17799 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17800 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
18248 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
18659 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5a9xx.h17339 #define XSPI_WCCR_IMODE_Pos (0U) macro
17340 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17342 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17343 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17344 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
17792 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
18203 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
Dstm32u5g9xx.h18244 #define XSPI_WCCR_IMODE_Pos (0U) macro
18245 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
18247 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
18248 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
18249 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00…
18697 #define OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
19108 #define HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13464 #define XSPI_WCCR_IMODE_Pos (0U) macro
13465 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
13467 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
13468 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
13469 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7s7xx.h14498 #define XSPI_WCCR_IMODE_Pos (0U) macro
14499 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
14501 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
14502 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
14503 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7s3xx.h14096 #define XSPI_WCCR_IMODE_Pos (0U) macro
14097 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
14099 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
14100 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
14101 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32h7r7xx.h13864 #define XSPI_WCCR_IMODE_Pos (0U) macro
13865 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
13867 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
13868 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
13869 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39502 #define XSPI_WCCR_IMODE_Pos (0U) macro
39503 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
39505 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
39506 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
39507 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n657xx.h41141 #define XSPI_WCCR_IMODE_Pos (0U) macro
41142 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
41144 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
41145 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
41146 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n655xx.h40752 #define XSPI_WCCR_IMODE_Pos (0U) macro
40753 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
40755 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
40756 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
40757 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
Dstm32n647xx.h39891 #define XSPI_WCCR_IMODE_Pos (0U) macro
39892 #define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
39894 #define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
39895 #define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
39896 #define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */