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Searched refs:XSPI_WCCR_DDTR_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13219 #define XSPI_WCCR_DDTR_Pos (27U) macro
13220 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
13672 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
14083 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5a5xx.h13668 #define XSPI_WCCR_DDTR_Pos (27U) macro
13669 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
14121 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
14532 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5f7xx.h14717 #define XSPI_WCCR_DDTR_Pos (27U) macro
14718 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
15170 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
15581 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u545xx.h12269 #define XSPI_WCCR_DDTR_Pos (27U) macro
12270 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
12688 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u535xx.h11869 #define XSPI_WCCR_DDTR_Pos (27U) macro
11870 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
12288 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u599xx.h16938 #define XSPI_WCCR_DDTR_Pos (27U) macro
16939 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
17391 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
17802 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5g7xx.h15166 #define XSPI_WCCR_DDTR_Pos (27U) macro
15167 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
15619 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
16030 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5f9xx.h17843 #define XSPI_WCCR_DDTR_Pos (27U) macro
17844 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
18296 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
18707 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5a9xx.h17387 #define XSPI_WCCR_DDTR_Pos (27U) macro
17388 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
17840 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
18251 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u5g9xx.h18292 #define XSPI_WCCR_DDTR_Pos (27U) macro
18293 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
18745 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
19156 #define HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u575xx.h12904 #define XSPI_WCCR_DDTR_Pos (27U) macro
12905 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
13323 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32u585xx.h13353 #define XSPI_WCCR_DDTR_Pos (27U) macro
13354 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08…
13772 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11177 #define XSPI_WCCR_DDTR_Pos (27U) macro
11178 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x080…
11589 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32h562xx.h11903 #define XSPI_WCCR_DDTR_Pos (27U) macro
11904 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x080…
12315 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32h533xx.h11586 #define XSPI_WCCR_DDTR_Pos (27U) macro
11587 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x080…
11998 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32h573xx.h14396 #define XSPI_WCCR_DDTR_Pos (27U) macro
14397 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x080…
14808 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
Dstm32h563xx.h13987 #define XSPI_WCCR_DDTR_Pos (27U) macro
13988 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x080…
14399 #define OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13512 #define XSPI_WCCR_DDTR_Pos (27U) macro
13513 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s7xx.h14546 #define XSPI_WCCR_DDTR_Pos (27U) macro
14547 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s3xx.h14144 #define XSPI_WCCR_DDTR_Pos (27U) macro
14145 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7r7xx.h13912 #define XSPI_WCCR_DDTR_Pos (27U) macro
13913 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39550 #define XSPI_WCCR_DDTR_Pos (27U) macro
39551 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n657xx.h41189 #define XSPI_WCCR_DDTR_Pos (27U) macro
41190 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n655xx.h40800 #define XSPI_WCCR_DDTR_Pos (27U) macro
40801 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n647xx.h39939 #define XSPI_WCCR_DDTR_Pos (27U) macro
39940 #define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */