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Searched refs:XSPI_WCCR_ADDTR_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13191 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13192 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
13644 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
14055 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5a5xx.h13640 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13641 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
14093 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
14504 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5f7xx.h14689 #define XSPI_WCCR_ADDTR_Pos (11U) macro
14690 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
15142 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
15553 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u545xx.h12241 #define XSPI_WCCR_ADDTR_Pos (11U) macro
12242 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
12660 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u535xx.h11841 #define XSPI_WCCR_ADDTR_Pos (11U) macro
11842 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
12260 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u599xx.h16910 #define XSPI_WCCR_ADDTR_Pos (11U) macro
16911 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
17363 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
17774 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5g7xx.h15138 #define XSPI_WCCR_ADDTR_Pos (11U) macro
15139 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
15591 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
16002 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5f9xx.h17815 #define XSPI_WCCR_ADDTR_Pos (11U) macro
17816 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
18268 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
18679 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5a9xx.h17359 #define XSPI_WCCR_ADDTR_Pos (11U) macro
17360 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
17812 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
18223 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u5g9xx.h18264 #define XSPI_WCCR_ADDTR_Pos (11U) macro
18265 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
18717 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
19128 #define HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u575xx.h12876 #define XSPI_WCCR_ADDTR_Pos (11U) macro
12877 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
13295 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32u585xx.h13325 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13326 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00…
13744 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11149 #define XSPI_WCCR_ADDTR_Pos (11U) macro
11150 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x000…
11561 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32h562xx.h11875 #define XSPI_WCCR_ADDTR_Pos (11U) macro
11876 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x000…
12287 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32h533xx.h11558 #define XSPI_WCCR_ADDTR_Pos (11U) macro
11559 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x000…
11970 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32h573xx.h14368 #define XSPI_WCCR_ADDTR_Pos (11U) macro
14369 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x000…
14780 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
Dstm32h563xx.h13959 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13960 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x000…
14371 #define OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13484 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13485 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32h7s7xx.h14518 #define XSPI_WCCR_ADDTR_Pos (11U) macro
14519 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32h7s3xx.h14116 #define XSPI_WCCR_ADDTR_Pos (11U) macro
14117 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32h7r7xx.h13884 #define XSPI_WCCR_ADDTR_Pos (11U) macro
13885 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39522 #define XSPI_WCCR_ADDTR_Pos (11U) macro
39523 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32n657xx.h41161 #define XSPI_WCCR_ADDTR_Pos (11U) macro
41162 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32n655xx.h40772 #define XSPI_WCCR_ADDTR_Pos (11U) macro
40773 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
Dstm32n647xx.h39911 #define XSPI_WCCR_ADDTR_Pos (11U) macro
39912 #define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */