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Searched refs:XSPI_TCR_DHQC_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13071 #define XSPI_TCR_DHQC_Pos (28U) macro
13072 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
13524 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
13935 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5a5xx.h13520 #define XSPI_TCR_DHQC_Pos (28U) macro
13521 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
13973 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
14384 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5f7xx.h14569 #define XSPI_TCR_DHQC_Pos (28U) macro
14570 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
15022 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
15433 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u545xx.h12121 #define XSPI_TCR_DHQC_Pos (28U) macro
12122 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
12540 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u535xx.h11721 #define XSPI_TCR_DHQC_Pos (28U) macro
11722 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
12140 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u599xx.h16790 #define XSPI_TCR_DHQC_Pos (28U) macro
16791 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
17243 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
17654 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5g7xx.h15018 #define XSPI_TCR_DHQC_Pos (28U) macro
15019 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
15471 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
15882 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5f9xx.h17695 #define XSPI_TCR_DHQC_Pos (28U) macro
17696 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
18148 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
18559 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5a9xx.h17239 #define XSPI_TCR_DHQC_Pos (28U) macro
17240 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
17692 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
18103 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u5g9xx.h18144 #define XSPI_TCR_DHQC_Pos (28U) macro
18145 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
18597 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
19008 #define HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u575xx.h12756 #define XSPI_TCR_DHQC_Pos (28U) macro
12757 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
13175 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32u585xx.h13205 #define XSPI_TCR_DHQC_Pos (28U) macro
13206 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10…
13624 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11029 #define XSPI_TCR_DHQC_Pos (28U) macro
11030 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x100…
11441 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32h562xx.h11755 #define XSPI_TCR_DHQC_Pos (28U) macro
11756 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x100…
12167 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32h533xx.h11438 #define XSPI_TCR_DHQC_Pos (28U) macro
11439 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x100…
11850 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32h573xx.h14248 #define XSPI_TCR_DHQC_Pos (28U) macro
14249 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x100…
14660 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
Dstm32h563xx.h13839 #define XSPI_TCR_DHQC_Pos (28U) macro
13840 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x100…
14251 #define OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13364 #define XSPI_TCR_DHQC_Pos (28U) macro
13365 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32h7s7xx.h14398 #define XSPI_TCR_DHQC_Pos (28U) macro
14399 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32h7s3xx.h13996 #define XSPI_TCR_DHQC_Pos (28U) macro
13997 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32h7r7xx.h13764 #define XSPI_TCR_DHQC_Pos (28U) macro
13765 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39402 #define XSPI_TCR_DHQC_Pos (28U) macro
39403 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32n657xx.h41041 #define XSPI_TCR_DHQC_Pos (28U) macro
41042 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32n655xx.h40652 #define XSPI_TCR_DHQC_Pos (28U) macro
40653 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
Dstm32n647xx.h39791 #define XSPI_TCR_DHQC_Pos (28U) macro
39792 #define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */