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Searched refs:XSPI_DCR2_WRAPSIZE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10882 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
10883 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
10885 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
10886 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
10887 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11294 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32h562xx.h11608 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
11609 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11611 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11612 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11613 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
12020 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32h533xx.h11291 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
11292 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11294 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11295 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11296 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
11703 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32h573xx.h14101 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
14102 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
14104 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
14105 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
14106 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
14513 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32h563xx.h13692 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13693 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
13695 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
13696 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
13697 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x000…
14104 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11972 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
11973 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11975 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11976 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11977 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12390 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u535xx.h11572 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
11573 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11575 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11576 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11577 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
11990 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u595xx.h12922 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
12923 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12925 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12926 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12927 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13374 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
13788 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5a5xx.h13371 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13372 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13374 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13375 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13376 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13823 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
14237 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5f7xx.h14420 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
14421 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14423 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14424 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14425 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14872 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
15286 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u575xx.h12607 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
12608 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12610 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12611 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
12612 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13025 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u599xx.h16641 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
16642 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
16644 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
16645 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
16646 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17093 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
17507 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5g7xx.h14869 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
14870 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14872 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14873 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
14874 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
15321 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
15735 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u585xx.h13056 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13057 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13059 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13060 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13061 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
13474 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5f9xx.h17546 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
17547 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17549 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17550 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17551 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17998 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
18412 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5a9xx.h17090 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
17091 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17093 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17094 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17095 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17542 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
17956 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
Dstm32u5g9xx.h17995 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
17996 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17998 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
17999 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
18000 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00…
18447 #define OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
18861 #define HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13217 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13218 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
13220 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
13221 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
13222 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32h7s7xx.h14251 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
14252 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
14254 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
14255 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
14256 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32h7s3xx.h13849 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13850 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
13852 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
13853 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
13854 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32h7r7xx.h13617 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
13618 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
13620 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
13621 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
13622 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39255 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
39256 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
39258 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
39259 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
39260 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32n657xx.h40894 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
40895 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
40897 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
40898 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
40899 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32n655xx.h40505 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
40506 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
40508 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
40509 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
40510 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
Dstm32n647xx.h39644 #define XSPI_DCR2_WRAPSIZE_Pos (16U) macro
39645 #define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
39647 #define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
39648 #define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
39649 #define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */