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Searched refs:XSPI_DCR1_MTYP_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10871 #define XSPI_DCR1_MTYP_Pos (24U) macro
10872 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x070…
10874 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x010…
10875 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020…
10876 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040…
11283 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32h562xx.h11597 #define XSPI_DCR1_MTYP_Pos (24U) macro
11598 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x070…
11600 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x010…
11601 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020…
11602 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040…
12009 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32h533xx.h11280 #define XSPI_DCR1_MTYP_Pos (24U) macro
11281 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x070…
11283 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x010…
11284 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020…
11285 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040…
11692 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32h573xx.h14090 #define XSPI_DCR1_MTYP_Pos (24U) macro
14091 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x070…
14093 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x010…
14094 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020…
14095 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040…
14502 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32h563xx.h13681 #define XSPI_DCR1_MTYP_Pos (24U) macro
13682 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x070…
13684 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x010…
13685 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x020…
13686 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x040…
14093 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h11961 #define XSPI_DCR1_MTYP_Pos (24U) macro
11962 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
11964 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
11965 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
11966 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
12379 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u535xx.h11561 #define XSPI_DCR1_MTYP_Pos (24U) macro
11562 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
11564 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
11565 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
11566 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
11979 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u595xx.h12911 #define XSPI_DCR1_MTYP_Pos (24U) macro
12912 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
12914 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
12915 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
12916 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
13363 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
13777 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5a5xx.h13360 #define XSPI_DCR1_MTYP_Pos (24U) macro
13361 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
13363 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
13364 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
13365 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
13812 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
14226 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5f7xx.h14409 #define XSPI_DCR1_MTYP_Pos (24U) macro
14410 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
14412 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
14413 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
14414 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
14861 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
15275 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u575xx.h12596 #define XSPI_DCR1_MTYP_Pos (24U) macro
12597 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
12599 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
12600 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
12601 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
13014 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u599xx.h16630 #define XSPI_DCR1_MTYP_Pos (24U) macro
16631 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
16633 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
16634 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
16635 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
17082 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
17496 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5g7xx.h14858 #define XSPI_DCR1_MTYP_Pos (24U) macro
14859 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
14861 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
14862 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
14863 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
15310 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
15724 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u585xx.h13045 #define XSPI_DCR1_MTYP_Pos (24U) macro
13046 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
13048 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
13049 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
13050 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
13463 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5f9xx.h17535 #define XSPI_DCR1_MTYP_Pos (24U) macro
17536 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
17538 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
17539 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
17540 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
17987 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
18401 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5a9xx.h17079 #define XSPI_DCR1_MTYP_Pos (24U) macro
17080 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
17082 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
17083 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
17084 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
17531 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
17945 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
Dstm32u5g9xx.h17984 #define XSPI_DCR1_MTYP_Pos (24U) macro
17985 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07…
17987 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01…
17988 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02…
17989 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04…
18436 #define OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
18850 #define HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13206 #define XSPI_DCR1_MTYP_Pos (24U) macro
13207 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
13209 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
13210 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
13211 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32h7s7xx.h14240 #define XSPI_DCR1_MTYP_Pos (24U) macro
14241 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
14243 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
14244 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
14245 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32h7s3xx.h13838 #define XSPI_DCR1_MTYP_Pos (24U) macro
13839 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
13841 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
13842 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
13843 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32h7r7xx.h13606 #define XSPI_DCR1_MTYP_Pos (24U) macro
13607 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
13609 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
13610 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
13611 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39244 #define XSPI_DCR1_MTYP_Pos (24U) macro
39245 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
39247 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
39248 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
39249 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32n657xx.h40883 #define XSPI_DCR1_MTYP_Pos (24U) macro
40884 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
40886 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
40887 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
40888 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32n655xx.h40494 #define XSPI_DCR1_MTYP_Pos (24U) macro
40495 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
40497 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
40498 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
40499 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
Dstm32n647xx.h39633 #define XSPI_DCR1_MTYP_Pos (24U) macro
39634 #define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
39636 #define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
39637 #define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
39638 #define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */