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Searched refs:XSPI_DCR1_CSHT_Pos (Results 1 – 25 of 29) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_xspi.c391 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_xspi.c406 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_xspi.c404 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_xspi.c434 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h12905 #define XSPI_DCR1_CSHT_Pos (8U) macro
12906 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
13357 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
13771 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5a5xx.h13354 #define XSPI_DCR1_CSHT_Pos (8U) macro
13355 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
13806 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
14220 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5f7xx.h14403 #define XSPI_DCR1_CSHT_Pos (8U) macro
14404 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
14855 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
15269 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u545xx.h11955 #define XSPI_DCR1_CSHT_Pos (8U) macro
11956 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
12373 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u535xx.h11555 #define XSPI_DCR1_CSHT_Pos (8U) macro
11556 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
11973 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u599xx.h16624 #define XSPI_DCR1_CSHT_Pos (8U) macro
16625 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
17076 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
17490 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5g7xx.h14852 #define XSPI_DCR1_CSHT_Pos (8U) macro
14853 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
15304 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
15718 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5f9xx.h17529 #define XSPI_DCR1_CSHT_Pos (8U) macro
17530 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
17981 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
18395 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5a9xx.h17073 #define XSPI_DCR1_CSHT_Pos (8U) macro
17074 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
17525 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
17939 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u5g9xx.h17978 #define XSPI_DCR1_CSHT_Pos (8U) macro
17979 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
18430 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
18844 #define HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u575xx.h12590 #define XSPI_DCR1_CSHT_Pos (8U) macro
12591 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
13008 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32u585xx.h13039 #define XSPI_DCR1_CSHT_Pos (8U) macro
13040 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00…
13457 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10865 #define XSPI_DCR1_CSHT_Pos (8U) macro
10866 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x000…
11277 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32h562xx.h11591 #define XSPI_DCR1_CSHT_Pos (8U) macro
11592 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x000…
12003 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32h533xx.h11274 #define XSPI_DCR1_CSHT_Pos (8U) macro
11275 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x000…
11686 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32h573xx.h14084 #define XSPI_DCR1_CSHT_Pos (8U) macro
14085 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x000…
14496 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
Dstm32h563xx.h13675 #define XSPI_DCR1_CSHT_Pos (8U) macro
13676 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x000…
14087 #define OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13200 #define XSPI_DCR1_CSHT_Pos (8U) macro
13201 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
Dstm32h7s7xx.h14234 #define XSPI_DCR1_CSHT_Pos (8U) macro
14235 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
Dstm32h7s3xx.h13832 #define XSPI_DCR1_CSHT_Pos (8U) macro
13833 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
Dstm32h7r7xx.h13600 #define XSPI_DCR1_CSHT_Pos (8U) macro
13601 #define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */

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