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Searched refs:XSPI_CCR_DDTR_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u595xx.h13057 #define XSPI_CCR_DDTR_Pos (27U) macro
13058 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
13510 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
13921 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5a5xx.h13506 #define XSPI_CCR_DDTR_Pos (27U) macro
13507 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
13959 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
14370 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5f7xx.h14555 #define XSPI_CCR_DDTR_Pos (27U) macro
14556 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
15008 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
15419 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u545xx.h12107 #define XSPI_CCR_DDTR_Pos (27U) macro
12108 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
12526 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u535xx.h11707 #define XSPI_CCR_DDTR_Pos (27U) macro
11708 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
12126 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u599xx.h16776 #define XSPI_CCR_DDTR_Pos (27U) macro
16777 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
17229 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
17640 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5g7xx.h15004 #define XSPI_CCR_DDTR_Pos (27U) macro
15005 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
15457 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
15868 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5f9xx.h17681 #define XSPI_CCR_DDTR_Pos (27U) macro
17682 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
18134 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
18545 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5a9xx.h17225 #define XSPI_CCR_DDTR_Pos (27U) macro
17226 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
17678 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
18089 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u5g9xx.h18130 #define XSPI_CCR_DDTR_Pos (27U) macro
18131 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
18583 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
18994 #define HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u575xx.h12742 #define XSPI_CCR_DDTR_Pos (27U) macro
12743 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
13161 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32u585xx.h13191 #define XSPI_CCR_DDTR_Pos (27U) macro
13192 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08…
13610 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11015 #define XSPI_CCR_DDTR_Pos (27U) macro
11016 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x080…
11427 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32h562xx.h11741 #define XSPI_CCR_DDTR_Pos (27U) macro
11742 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x080…
12153 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32h533xx.h11424 #define XSPI_CCR_DDTR_Pos (27U) macro
11425 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x080…
11836 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32h573xx.h14234 #define XSPI_CCR_DDTR_Pos (27U) macro
14235 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x080…
14646 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
Dstm32h563xx.h13825 #define XSPI_CCR_DDTR_Pos (27U) macro
13826 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x080…
14237 #define OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13353 #define XSPI_CCR_DDTR_Pos (27U) macro
13354 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s7xx.h14387 #define XSPI_CCR_DDTR_Pos (27U) macro
14388 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7s3xx.h13985 #define XSPI_CCR_DDTR_Pos (27U) macro
13986 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32h7r7xx.h13753 #define XSPI_CCR_DDTR_Pos (27U) macro
13754 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39391 #define XSPI_CCR_DDTR_Pos (27U) macro
39392 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n657xx.h41030 #define XSPI_CCR_DDTR_Pos (27U) macro
41031 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n655xx.h40641 #define XSPI_CCR_DDTR_Pos (27U) macro
40642 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
Dstm32n647xx.h39780 #define XSPI_CCR_DDTR_Pos (27U) macro
39781 #define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */