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Searched refs:XSPI_CCR_ADSIZE_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h10990 #define XSPI_CCR_ADSIZE_Pos (12U) macro
10991 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
10993 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
10994 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11402 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32h562xx.h11716 #define XSPI_CCR_ADSIZE_Pos (12U) macro
11717 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11719 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11720 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
12128 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32h533xx.h11399 #define XSPI_CCR_ADSIZE_Pos (12U) macro
11400 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11402 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11403 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
11811 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32h573xx.h14209 #define XSPI_CCR_ADSIZE_Pos (12U) macro
14210 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
14212 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
14213 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
14621 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32h563xx.h13800 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13801 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
13803 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
13804 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x000…
14212 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12082 #define XSPI_CCR_ADSIZE_Pos (12U) macro
12083 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12085 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12086 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12501 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u535xx.h11682 #define XSPI_CCR_ADSIZE_Pos (12U) macro
11683 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
11685 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
11686 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12101 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u595xx.h13032 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13033 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13035 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13036 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13485 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
13896 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5a5xx.h13481 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13482 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13484 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13485 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13934 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
14345 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5f7xx.h14530 #define XSPI_CCR_ADSIZE_Pos (12U) macro
14531 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
14533 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
14534 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
14983 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
15394 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u575xx.h12717 #define XSPI_CCR_ADSIZE_Pos (12U) macro
12718 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12720 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
12721 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13136 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u599xx.h16751 #define XSPI_CCR_ADSIZE_Pos (12U) macro
16752 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
16754 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
16755 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17204 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
17615 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5g7xx.h14979 #define XSPI_CCR_ADSIZE_Pos (12U) macro
14980 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
14982 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
14983 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
15432 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
15843 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5f9xx.h17656 #define XSPI_CCR_ADSIZE_Pos (12U) macro
17657 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17659 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17660 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
18109 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
18520 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5a9xx.h17200 #define XSPI_CCR_ADSIZE_Pos (12U) macro
17201 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17203 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17204 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
17653 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
18064 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u5g9xx.h18105 #define XSPI_CCR_ADSIZE_Pos (12U) macro
18106 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
18108 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
18109 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
18558 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
18969 #define HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
Dstm32u585xx.h13166 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13167 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13169 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13170 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00…
13585 #define OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h13328 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13329 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13331 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13332 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32h7s7xx.h14362 #define XSPI_CCR_ADSIZE_Pos (12U) macro
14363 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
14365 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
14366 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32h7s3xx.h13960 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13961 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13963 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13964 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32h7r7xx.h13728 #define XSPI_CCR_ADSIZE_Pos (12U) macro
13729 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13731 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13732 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h39366 #define XSPI_CCR_ADSIZE_Pos (12U) macro
39367 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
39369 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
39370 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32n657xx.h41005 #define XSPI_CCR_ADSIZE_Pos (12U) macro
41006 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
41008 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
41009 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32n655xx.h40616 #define XSPI_CCR_ADSIZE_Pos (12U) macro
40617 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
40619 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
40620 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
Dstm32n647xx.h39755 #define XSPI_CCR_ADSIZE_Pos (12U) macro
39756 #define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
39758 #define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
39759 #define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */