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Searched refs:WRITE_REG (Results 1 – 25 of 1245) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_bus.h337 WRITE_REG(RCC->MC_AHB2ENSETR, Periphs); in LL_AHB2_GRP1_EnableClock()
384 WRITE_REG(RCC->MC_AHB2ENCLRR, Periphs); in LL_AHB2_GRP1_DisableClock()
407 WRITE_REG(RCC->AHB2RSTSETR, Periphs); in LL_AHB2_GRP1_ForceReset()
430 WRITE_REG(RCC->AHB2RSTCLRR, Periphs); in LL_AHB2_GRP1_ReleaseReset()
453 WRITE_REG(RCC->MC_AHB2LPENSETR, Periphs); in LL_AHB2_GRP1_EnableClockSleep()
478 WRITE_REG(RCC->MC_AHB2LPENCLRR, Periphs); in LL_AHB2_GRP1_DisableClockSleep()
513 WRITE_REG(RCC->MC_AHB3ENSETR, Periphs); in LL_AHB3_GRP1_EnableClock()
568 WRITE_REG(RCC->MC_AHB3ENCLRR, Periphs); in LL_AHB3_GRP1_DisableClock()
595 WRITE_REG(RCC->AHB3RSTSETR, Periphs); in LL_AHB3_GRP1_ForceReset()
622 WRITE_REG(RCC->AHB3RSTCLRR, Periphs); in LL_AHB3_GRP1_ReleaseReset()
[all …]
Dstm32mp1xx_ll_dma.h372 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VAL…
1668 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddres… in LL_DMA_ConfigAddresses()
1669 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress… in LL_DMA_ConfigAddresses()
1674 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress… in LL_DMA_ConfigAddresses()
1675 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddres… in LL_DMA_ConfigAddresses()
1701 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAdd… in LL_DMA_SetMemoryAddress()
1726 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddr… in LL_DMA_SetPeriphAddress()
1797 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddr… in LL_DMA_SetM2MSrcAddress()
1822 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAdd… in LL_DMA_SetM2MDstAddress()
2372 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); in LL_DMA_ClearFlag_HT0()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h452 WRITE_REG(RCC->BUSENSR, Bus); in LL_BUS_EnableClock()
527 WRITE_REG(RCC->BUSENCR, Bus); in LL_BUS_DisableClock()
564 WRITE_REG(RCC->BUSLPENSR, Bus); in LL_BUS_EnableClockLowPower()
639 WRITE_REG(RCC->BUSLPENCR, Bus); in LL_BUS_DisableClockLowPower()
682 WRITE_REG(RCC->MEMENSR, Memories); in LL_MEM_EnableClock()
753 WRITE_REG(RCC->MEMENCR, Memories); in LL_MEM_DisableClock()
788 WRITE_REG(RCC->MEMLPENSR, Memories); in LL_MEM_EnableClockLowPower()
859 WRITE_REG(RCC->MEMLPENCR, Memories); in LL_MEM_DisableClockLowPower()
882 WRITE_REG(RCC->AHB1ENSR, Periphs); in LL_AHB1_GRP1_EnableClock()
913 WRITE_REG(RCC->AHB1ENCR, Periphs); in LL_AHB1_GRP1_DisableClock()
[all …]
Dstm32n6xx_ll_cortex.h538 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
556 WRITE_REG(MPU_NS->CTRL, 0U); in LL_MPU_Disable_NS()
612 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
644 WRITE_REG(MPU->RNR, Region); in LL_MPU_IsEnabledRegion()
677 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_EnableRegion_NS()
709 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_IsEnabledRegion_NS()
743 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
777 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_DisableRegion_NS()
835 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
838 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); in LL_MPU_ConfigRegion()
[all …]
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_dma.h346 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
934 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress); in LL_DMA_ConfigAddresses()
935 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress); in LL_DMA_ConfigAddresses()
940 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress); in LL_DMA_ConfigAddresses()
941 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress); in LL_DMA_ConfigAddresses()
965 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); in LL_DMA_SetMemoryAddress()
988 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); in LL_DMA_SetPeriphAddress()
1053 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); in LL_DMA_SetM2MSrcAddress()
1076 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); in LL_DMA_SetM2MDstAddress()
1532 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_cortex.h559 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
578 WRITE_REG(MPU_NS->CTRL, 0U); in LL_MPU_Disable_NS()
633 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
662 WRITE_REG(MPU->RNR, Region); in LL_MPU_IsEnabled_Region()
687 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_EnableRegion_NS()
711 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_IsEnabled_Region_NS()
742 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
768 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_DisableRegion_NS()
823 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
826 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); in LL_MPU_ConfigRegion()
[all …]
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_cortex.h556 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
575 WRITE_REG(MPU_NS->CTRL, 0U); in LL_MPU_Disable_NS()
625 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
649 WRITE_REG(MPU->RNR, Region); in LL_MPU_IsEnabled_Region()
674 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_EnableRegion_NS()
698 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_IsEnabled_Region_NS()
724 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
750 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_DisableRegion_NS()
800 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
803 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); in LL_MPU_ConfigRegion()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_cortex.h552 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
571 WRITE_REG(MPU_NS->CTRL, 0U); in LL_MPU_Disable_NS()
621 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
645 WRITE_REG(MPU->RNR, Region); in LL_MPU_IsEnabled_Region()
670 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_EnableRegion_NS()
694 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_IsEnabled_Region_NS()
720 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
746 WRITE_REG(MPU_NS->RNR, Region); in LL_MPU_DisableRegion_NS()
796 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
799 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); in LL_MPU_ConfigRegion()
[all …]
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_ll_dma.h382 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1397 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, S… in LL_DMA_ConfigAddresses()
1398 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Ds… in LL_DMA_ConfigAddresses()
1403 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Sr… in LL_DMA_ConfigAddresses()
1404 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, D… in LL_DMA_ConfigAddresses()
1428 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetMemoryAddress()
1451 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Pe… in LL_DMA_SetPeriphAddress()
1516 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Me… in LL_DMA_SetM2MSrcAddress()
1539 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetM2MDstAddress()
2081 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); in LL_DMA_ClearFlag_HT0()
[all …]
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_dma.h395 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1430 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, S… in LL_DMA_ConfigAddresses()
1431 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Ds… in LL_DMA_ConfigAddresses()
1436 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Sr… in LL_DMA_ConfigAddresses()
1437 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, D… in LL_DMA_ConfigAddresses()
1461 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetMemoryAddress()
1484 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Pe… in LL_DMA_SetPeriphAddress()
1549 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Me… in LL_DMA_SetM2MSrcAddress()
1572 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetM2MDstAddress()
2114 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); in LL_DMA_ClearFlag_HT0()
[all …]
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_dma.h392 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1407 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, S… in LL_DMA_ConfigAddresses()
1408 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Ds… in LL_DMA_ConfigAddresses()
1413 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Sr… in LL_DMA_ConfigAddresses()
1414 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, D… in LL_DMA_ConfigAddresses()
1438 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetMemoryAddress()
1461 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Pe… in LL_DMA_SetPeriphAddress()
1526 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, Me… in LL_DMA_SetM2MSrcAddress()
1549 …WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, M… in LL_DMA_SetM2MDstAddress()
2091 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); in LL_DMA_ClearFlag_HT0()
[all …]
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_cortex.h527 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
564 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
610 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
659 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
662 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); in LL_MPU_ConfigRegion()
665 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); in LL_MPU_ConfigRegion()
690 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegionAddress()
757 WRITE_REG(MPU->RNR, Region); in LL_MPU_SetRegionBaseAddress()
781 WRITE_REG(MPU->RNR, Region); in LL_MPU_GetRegionBaseAddress()
806 WRITE_REG(MPU->RNR, Region); in LL_MPU_SetRegionLimitAddress()
[all …]
Dstm32l5xx_ll_dma.h404 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1466 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, SrcAddres… in LL_DMA_ConfigAddresses()
1467 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress… in LL_DMA_ConfigAddresses()
1472 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress… in LL_DMA_ConfigAddresses()
1473 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, DstAddres… in LL_DMA_ConfigAddresses()
1498 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAdd… in LL_DMA_SetMemoryAddress()
1522 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddr… in LL_DMA_SetPeriphAddress()
1590 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddr… in LL_DMA_SetM2MSrcAddress()
1614 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM0AR, MemoryAdd… in LL_DMA_SetM2MDstAddress()
1917 …WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CM1AR, MemoryAdd… in LL_DMA_SetMemory1Address()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_eth_ex.c122 WRITE_REG(heth->Instance->MACARPAR, IpAddress); in HAL_ETHEx_SetARPAddressMatch()
154 …WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
165 …WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
272 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
274 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]); in HAL_ETHEx_SetL3FilterConfig()
276 WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]); in HAL_ETHEx_SetL3FilterConfig()
278 WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]); in HAL_ETHEx_SetL3FilterConfig()
283 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr); in HAL_ETHEx_SetL3FilterConfig()
285 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr); in HAL_ETHEx_SetL3FilterConfig()
295 WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_eth_ex.c122 WRITE_REG(heth->Instance->MACARPAR, IpAddress); in HAL_ETHEx_SetARPAddressMatch()
154 …WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
165 …WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
272 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
274 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]); in HAL_ETHEx_SetL3FilterConfig()
276 WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]); in HAL_ETHEx_SetL3FilterConfig()
278 WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]); in HAL_ETHEx_SetL3FilterConfig()
283 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr); in HAL_ETHEx_SetL3FilterConfig()
285 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr); in HAL_ETHEx_SetL3FilterConfig()
295 WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_eth_ex.c122 WRITE_REG(heth->Instance->MACARPAR, IpAddress); in HAL_ETHEx_SetARPAddressMatch()
154 …WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
165 …WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPo… in HAL_ETHEx_SetL4FilterConfig()
272 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
274 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]); in HAL_ETHEx_SetL3FilterConfig()
276 WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]); in HAL_ETHEx_SetL3FilterConfig()
278 WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]); in HAL_ETHEx_SetL3FilterConfig()
283 WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr); in HAL_ETHEx_SetL3FilterConfig()
285 WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr); in HAL_ETHEx_SetL3FilterConfig()
295 WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]); in HAL_ETHEx_SetL3FilterConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_dma.h387 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VAL…
1811 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddres… in LL_DMA_ConfigAddresses()
1812 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress… in LL_DMA_ConfigAddresses()
1817 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress… in LL_DMA_ConfigAddresses()
1818 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddres… in LL_DMA_ConfigAddresses()
1844 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAdd… in LL_DMA_SetMemoryAddress()
1869 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddr… in LL_DMA_SetPeriphAddress()
1940 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddr… in LL_DMA_SetM2MSrcAddress()
1965 …WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAdd… in LL_DMA_SetM2MDstAddress()
2515 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); in LL_DMA_ClearFlag_HT0()
[all …]
Dstm32h7xx_ll_bdma.h373 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VA…
1165 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcA… in LL_BDMA_ConfigAddresses()
1166 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAd… in LL_BDMA_ConfigAddresses()
1171 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAd… in LL_BDMA_ConfigAddresses()
1172 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstA… in LL_BDMA_ConfigAddresses()
1198 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, Memo… in LL_BDMA_SetMemoryAddress()
1223 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, Perip… in LL_BDMA_SetPeriphAddress()
1294 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, Memor… in LL_BDMA_SetM2MSrcAddress()
1319 …WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, Memo… in LL_BDMA_SetM2MDstAddress()
1873 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0); in LL_BDMA_ClearFlag_GI0()
[all …]
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_dma.h333 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
936 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
937 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
942 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
943 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
966 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetMemoryAddress()
988 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetPeriphAddress()
1050 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MSrcAddress()
1072 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MDstAddress()
1439 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_dma.h391 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
990 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
991 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
996 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
997 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_ConfigAddresses()
1020 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetMemoryAddress()
1042 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetPeriphAddress()
1104 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MSrcAddress()
1126 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))… in LL_DMA_SetM2MDstAddress()
1595 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_dma.h350 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
987 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, SrcAddress); in LL_DMA_ConfigAddresses()
988 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, DstAddress); in LL_DMA_ConfigAddresses()
993 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, SrcAddress); in LL_DMA_ConfigAddresses()
994 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, DstAddress); in LL_DMA_ConfigAddresses()
1017 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); in LL_DMA_SetMemoryAddress()
1039 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); in LL_DMA_SetPeriphAddress()
1101 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); in LL_DMA_SetM2MSrcAddress()
1123 WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); in LL_DMA_SetM2MDstAddress()
1619 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_mce.c195 WRITE_REG(hmce->Instance->IACR, MCE_IACR_IAEF); in HAL_MCE_DeInit()
261 WRITE_REG(hmce->Instance->MKEYR0, 0U); in HAL_MCE_ConfigNoekeon()
265 WRITE_REG(hmce->Instance->MKEYR0, pConfig->pKey[0]); in HAL_MCE_ConfigNoekeon()
266 WRITE_REG(hmce->Instance->MKEYR1, pConfig->pKey[1]); in HAL_MCE_ConfigNoekeon()
267 WRITE_REG(hmce->Instance->MKEYR2, pConfig->pKey[2]); in HAL_MCE_ConfigNoekeon()
268 WRITE_REG(hmce->Instance->MKEYR3, pConfig->pKey[3]); in HAL_MCE_ConfigNoekeon()
269 WRITE_REG(hmce->Instance->MKEYR4, pConfig->pKey[4]); in HAL_MCE_ConfigNoekeon()
270 WRITE_REG(hmce->Instance->MKEYR5, pConfig->pKey[5]); in HAL_MCE_ConfigNoekeon()
271 WRITE_REG(hmce->Instance->MKEYR6, pConfig->pKey[6]); in HAL_MCE_ConfigNoekeon()
272 WRITE_REG(hmce->Instance->MKEYR7, pConfig->pKey[7]); in HAL_MCE_ConfigNoekeon()
[all …]
Dstm32n6xx_ll_pwr.c57 WRITE_REG(PWR->CR1, 0x00000024U); in LL_PWR_DeInit()
58 WRITE_REG(PWR->CR2, 0x00000000U); in LL_PWR_DeInit()
59 WRITE_REG(PWR->CR3, 0x00000000U); in LL_PWR_DeInit()
60 WRITE_REG(PWR->CR4, 0x00000000U); in LL_PWR_DeInit()
61 WRITE_REG(PWR->VOSCR, 0x00020002U); in LL_PWR_DeInit()
62 WRITE_REG(PWR->BDCR1, 0x00000000U); in LL_PWR_DeInit()
63 WRITE_REG(PWR->BDCR2, 0x00000000U); in LL_PWR_DeInit()
64 WRITE_REG(PWR->DBPCR, 0x00000000U); in LL_PWR_DeInit()
65 WRITE_REG(PWR->CPUCR, 0x00010000U); in LL_PWR_DeInit()
66 WRITE_REG(PWR->SVMCR1, 0x00000000U); in LL_PWR_DeInit()
[all …]
Dstm32n6xx_ll_rcc.c172 WRITE_REG(RCC->CIER, RCC_CIER_HSECSSIE); in LL_RCC_DeInit()
175 …WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | R… in LL_RCC_DeInit()
194 WRITE_REG(RCC->CCR, RCC_CCR_MSIONC | RCC_CCR_HSEONC | \ in LL_RCC_DeInit()
223 WRITE_REG(RCC->HSIMCR, 0x001F07A1U); in LL_RCC_DeInit()
226 WRITE_REG(RCC->HSECFGR, 0x00000800U); in LL_RCC_DeInit()
229 WRITE_REG(RCC->STOPCR, 0x00000008U); in LL_RCC_DeInit()
232 WRITE_REG(RCC->PLL1CFGR1, 0x08202500U); in LL_RCC_DeInit()
233 WRITE_REG(RCC->PLL1CFGR2, 0x00800000U); in LL_RCC_DeInit()
234 WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU); in LL_RCC_DeInit()
236 WRITE_REG(RCC->PLL2CFGR1, 0x08000000U); in LL_RCC_DeInit()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_dma.h380 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE…
1062 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR… in LL_DMA_ConfigAddresses()
1063 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR… in LL_DMA_ConfigAddresses()
1068 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR… in LL_DMA_ConfigAddresses()
1069 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR… in LL_DMA_ConfigAddresses()
1095 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR… in LL_DMA_SetMemoryAddress()
1120 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR… in LL_DMA_SetPeriphAddress()
1191 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR… in LL_DMA_SetM2MSrcAddress()
1216 …WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR… in LL_DMA_SetM2MDstAddress()
1945 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); in LL_DMA_ClearFlag_GI1()
[all …]

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