1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28 (+) API to enable fault handler (SHCSR accesses)
29 (+) API to enable and disable the MPU secure and non-secure
30 (+) API to configure the region of MPU secure and non-secure
31 (+) API to configure the attributes region of MPU secure and non-secure
32
33 @endverbatim
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32N6xx_LL_CORTEX_H
38 #define STM32N6xx_LL_CORTEX_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32n6xx.h"
46
47 /** @addtogroup STM32N6xx_LL_Driver
48 * @{
49 */
50
51 /** @defgroup CORTEX_LL CORTEX
52 * @{
53 */
54
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
59 * @{
60 */
61 /* Register MPU_RBAR (Cortex-M55) : bits [4:0] */
62 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
63 /**
64 * @}
65 */
66
67 /* Private macros ------------------------------------------------------------*/
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
71 * @{
72 */
73
74 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK CORTEX LL SYSTICK Clock Source
75 * @{
76 */
77 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0U /*!< AHB clock divided by 8 selected as SysTick
78 clock source */
79 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
80 clock source */
81 /**
82 * @}
83 */
84
85 /** @defgroup CORTEX_LL_EC_FAULT CORTEX LL Handler Fault type
86 * @{
87 */
88 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
89 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
90 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
91 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
92 /**
93 * @}
94 */
95
96 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
97 * @{
98 */
99 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Disable NMI and privileged SW access */
100 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
101 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
102 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
103 /**
104 * @}
105 */
106
107 /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
108 * @{
109 */
110 #define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
111 #define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
112 #define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
113 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
114
115 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
116 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
117 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
118
119 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
120 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
121
122 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
123 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
124 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
125 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
126 /**
127 * @}
128 */
129
130 /** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
131 * @{
132 */
133 #define LL_MPU_REGION_ENABLE 1U
134 #define LL_MPU_REGION_DISABLE 0U
135 /**
136 * @}
137 */
138
139 /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
140 * @{
141 */
142 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
143 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
144 /**
145 * @}
146 */
147
148 /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
149 * @{
150 */
151 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
152 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos)
153 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
154 /**
155 * @}
156 */
157
158 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
159 * @{
160 */
161 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
162 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
163 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
164 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
165 /**
166 * @}
167 */
168
169 /** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
170 * @{
171 */
172 #define LL_MPU_REGION_NUMBER0 0U
173 #define LL_MPU_REGION_NUMBER1 1U
174 #define LL_MPU_REGION_NUMBER2 2U
175 #define LL_MPU_REGION_NUMBER3 3U
176 #define LL_MPU_REGION_NUMBER4 4U
177 #define LL_MPU_REGION_NUMBER5 5U
178 #define LL_MPU_REGION_NUMBER6 6U
179 #define LL_MPU_REGION_NUMBER7 7U
180 #define LL_MPU_REGION_NUMBER8 8U
181 #define LL_MPU_REGION_NUMBER9 9U
182 #define LL_MPU_REGION_NUMBER10 10U
183 #define LL_MPU_REGION_NUMBER11 11U
184 #define LL_MPU_REGION_NUMBER12 12U
185 #define LL_MPU_REGION_NUMBER13 13U
186 #define LL_MPU_REGION_NUMBER14 14U
187 #define LL_MPU_REGION_NUMBER15 15U
188 /**
189 * @}
190 */
191
192 /** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
193 * @{
194 */
195 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
196 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
197 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
198 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
199 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
200 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
201 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
202 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
203 /**
204 * @}
205 */
206
207 /**
208 * @}
209 */
210
211 /* Exported macro ------------------------------------------------------------*/
212
213 /* Exported functions --------------------------------------------------------*/
214 /** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
215 * @{
216 */
217
218 /** @defgroup CORTEX_LL_EF_SYSTICK CORTEX LL SYSTICK
219 * @brief CORTEX SYSTICK LL module driver
220 * @{
221 */
222
223 /**
224 * @brief This function checks if the Systick counter flag is active or not.
225 * @note It can be used in timeout function on application side.
226 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
227 * @retval State of bit (1 or 0).
228 */
LL_SYSTICK_IsActiveCounterFlag(void)229 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
230 {
231 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
232 }
233
234 /**
235 * @brief Configures the SysTick clock source
236 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
237 * @param Source This parameter can be one of the following values:
238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
239 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
240 * @retval None
241 */
LL_SYSTICK_SetClkSource(uint32_t Source)242 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
243 {
244 MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
245 }
246
247 /**
248 * @brief Get the SysTick clock source
249 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
250 * @retval Returned value can be one of the following values:
251 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
252 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
253 */
LL_SYSTICK_GetClkSource(void)254 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
255 {
256 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
257 }
258
259 /**
260 * @brief Enable SysTick exception request
261 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
262 * @retval None
263 */
LL_SYSTICK_EnableIT(void)264 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
265 {
266 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
267 }
268
269 /**
270 * @brief Disable SysTick exception request
271 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
272 * @retval None
273 */
LL_SYSTICK_DisableIT(void)274 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
275 {
276 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
277 }
278
279 /**
280 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
281 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
282 * @retval State of bit (1 or 0).
283 */
LL_SYSTICK_IsEnabledIT(void)284 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
285 {
286 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
287 }
288
289 /**
290 * @}
291 */
292
293 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
294 * @{
295 */
296
297 /**
298 * @brief Processor uses sleep as its low power mode
299 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
300 * @retval None
301 */
LL_LPM_EnableSleep(void)302 __STATIC_INLINE void LL_LPM_EnableSleep(void)
303 {
304 /* Clear SLEEPDEEP bit of Cortex System Control Register */
305 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
306 }
307
308 /**
309 * @brief Processor uses deep sleep as its low power mode
310 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
311 * @retval None
312 */
LL_LPM_EnableDeepSleep(void)313 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
314 {
315 /* Set SLEEPDEEP bit of Cortex System Control Register */
316 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
317 }
318
319 /**
320 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
321 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
322 * empty main application.
323 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
324 * @retval None
325 */
LL_LPM_EnableSleepOnExit(void)326 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
327 {
328 /* Set SLEEPONEXIT bit of Cortex System Control Register */
329 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
330 }
331
332 /**
333 * @brief Do not sleep when returning to Thread mode.
334 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
335 * @retval None
336 */
LL_LPM_DisableSleepOnExit(void)337 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
338 {
339 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
340 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
341 }
342
343 /**
344 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
345 * processor.
346 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
347 * @retval None
348 */
LL_LPM_EnableEventOnPend(void)349 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
350 {
351 /* Set SEVEONPEND bit of Cortex System Control Register */
352 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
353 }
354
355 /**
356 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
357 * excluded
358 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
359 * @retval None
360 */
LL_LPM_DisableEventOnPend(void)361 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
362 {
363 /* Clear SEVEONPEND bit of Cortex System Control Register */
364 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
365 }
366
367 /**
368 * @}
369 */
370
371 /** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
372 * @{
373 */
374
375 /**
376 * @brief Enable a fault in System handler control register (SHCSR)
377 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
378 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
379 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
380 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
381 * @param Fault This parameter can be a combination of the following values:
382 * @arg @ref LL_HANDLER_FAULT_USG
383 * @arg @ref LL_HANDLER_FAULT_BUS
384 * @arg @ref LL_HANDLER_FAULT_MEM
385 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
386 *
387 * (*) value applicable in secure when the system implements the security.
388 * @retval None
389 */
LL_HANDLER_EnableFault(uint32_t Fault)390 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
391 {
392 /* Enable the system handler fault */
393 SET_BIT(SCB->SHCSR, Fault);
394 }
395
396 /**
397 * @brief Disable a fault in System handler control register (SHCSR)
398 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
399 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
400 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
401 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
402 * @param Fault This parameter can be a combination of the following values:
403 * @arg @ref LL_HANDLER_FAULT_USG
404 * @arg @ref LL_HANDLER_FAULT_BUS
405 * @arg @ref LL_HANDLER_FAULT_MEM
406 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
407 *
408 * (*) value applicable in secure when the system implements the security.
409 * @retval None
410 */
LL_HANDLER_DisableFault(uint32_t Fault)411 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
412 {
413 /* Disable the system handler fault */
414 CLEAR_BIT(SCB->SHCSR, Fault);
415 }
416
417 /**
418 * @}
419 */
420
421 /** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
422 * @{
423 */
424
425 /**
426 * @brief Get Implementer code
427 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
428 * @retval Value should be equal to 0x41 for ARM
429 */
LL_CPUID_GetImplementer(void)430 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
431 {
432 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
433 }
434
435 /**
436 * @brief Get Variant number (The r value in the rnpn product revision identifier)
437 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
438 * @retval Value between 0 and 255 (0x0: revision 0)
439 */
LL_CPUID_GetVariant(void)440 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
441 {
442 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
443 }
444
445 /**
446 * @brief Get Architecture version
447 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
448 * @retval Value should be equal to 0xF for Cortex-M55 ("ARMv8-M with Main Extension")
449 */
LL_CPUID_GetArchitecture(void)450 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
451 {
452 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
453 }
454
455 /**
456 * @brief Get Part number
457 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
458 * @retval Value should be equal to 0xD22 for Cortex-M55
459 */
LL_CPUID_GetParNo(void)460 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
461 {
462 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
463 }
464
465 /**
466 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
467 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
468 * @retval Value between 0 and 255 (0x1: patch 1)
469 */
LL_CPUID_GetRevision(void)470 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
471 {
472 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
473 }
474
475 /**
476 * @}
477 */
478
479 /** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
480 * @{
481 */
482
483 /**
484 * @brief Enable MPU with input options
485 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
486 * @param MPU_Control This parameter can be one of the following values:
487 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
488 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
489 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
490 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
491 * @retval None
492 */
LL_MPU_Enable(uint32_t MPU_Control)493 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
494 {
495 __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
496
497 /* Enable the MPU */
498 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
499
500 /* Ensure MPU settings take effects */
501 __DSB();
502 __ISB();
503 }
504
505 #ifdef MPU_NS
506 /**
507 * @brief Enable non-secure MPU with input options
508 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
509 * @param MPU_Control This parameter can be one of the following values:
510 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
511 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
512 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
513 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
514 * @retval None
515 */
LL_MPU_Enable_NS(uint32_t MPU_Control)516 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
517 {
518 __DMB(); /* Force any outstanding transfers to complete before enabling MPU */
519 /* Enable the MPU */
520 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
521
522 /* Ensure MPU settings take effects */
523 __DSB();
524 __ISB();
525 }
526 #endif /* MPU_NS */
527
528 /**
529 * @brief Disable MPU
530 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
531 * @retval None
532 */
LL_MPU_Disable(void)533 __STATIC_INLINE void LL_MPU_Disable(void)
534 {
535 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
536
537 /* Disable MPU_NS */
538 WRITE_REG(MPU->CTRL, 0U);
539
540 /* Ensure MPU settings take effects */
541 __DSB();
542 __ISB();
543 }
544
545 #ifdef MPU_NS
546 /**
547 * @brief Disable the non-secure MPU
548 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
549 * @retval None
550 */
LL_MPU_Disable_NS(void)551 __STATIC_INLINE void LL_MPU_Disable_NS(void)
552 {
553 __DMB(); /* Force any outstanding transfers to complete before disabling MPU */
554
555 /* Disable MPU_NS */
556 WRITE_REG(MPU_NS->CTRL, 0U);
557
558 /* Ensure MPU settings take effects */
559 __DSB();
560 __ISB();
561 }
562 #endif /* MPU_NS */
563
564 /**
565 * @brief Check if MPU is enabled or not
566 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
567 * @retval State of bit (1 or 0).
568 */
LL_MPU_IsEnabled(void)569 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
570 {
571 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
572 }
573
574 #ifdef MPU_NS
575 /**
576 * @brief Check if non-secure MPU is enabled or not
577 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
578 * @retval State of bit (1 or 0).
579 */
LL_MPU_IsEnabled_NS(void)580 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
581 {
582 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
583 }
584 #endif /* MPU_NS */
585
586 /**
587 * @brief Enable a MPU region
588 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion
589 * @param Region This parameter can be one of the following values:
590 * @arg @ref LL_MPU_REGION_NUMBER0
591 * @arg @ref LL_MPU_REGION_NUMBER1
592 * @arg @ref LL_MPU_REGION_NUMBER2
593 * @arg @ref LL_MPU_REGION_NUMBER3
594 * @arg @ref LL_MPU_REGION_NUMBER4
595 * @arg @ref LL_MPU_REGION_NUMBER5
596 * @arg @ref LL_MPU_REGION_NUMBER6
597 * @arg @ref LL_MPU_REGION_NUMBER7
598 * @arg @ref LL_MPU_REGION_NUMBER8
599 * @arg @ref LL_MPU_REGION_NUMBER9
600 * @arg @ref LL_MPU_REGION_NUMBER10
601 * @arg @ref LL_MPU_REGION_NUMBER11
602 * @arg @ref LL_MPU_REGION_NUMBER12
603 * @arg @ref LL_MPU_REGION_NUMBER13
604 * @arg @ref LL_MPU_REGION_NUMBER14
605 * @arg @ref LL_MPU_REGION_NUMBER15
606 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
607 * @retval None
608 */
LL_MPU_EnableRegion(uint32_t Region)609 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
610 {
611 /* Set Region number */
612 WRITE_REG(MPU->RNR, Region);
613
614 /* Enable the MPU region */
615 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
616 }
617
618 /**
619 * @brief Check if MPU region is enabled or not
620 * @rmtoll MPU_RNR EN LL_MPU_IsEnabledRegion
621 * @param Region This parameter can be one of the following values:
622 * @arg @ref LL_MPU_REGION_NUMBER0
623 * @arg @ref LL_MPU_REGION_NUMBER1
624 * @arg @ref LL_MPU_REGION_NUMBER2
625 * @arg @ref LL_MPU_REGION_NUMBER3
626 * @arg @ref LL_MPU_REGION_NUMBER4
627 * @arg @ref LL_MPU_REGION_NUMBER5
628 * @arg @ref LL_MPU_REGION_NUMBER6
629 * @arg @ref LL_MPU_REGION_NUMBER7
630 * @arg @ref LL_MPU_REGION_NUMBER8
631 * @arg @ref LL_MPU_REGION_NUMBER9
632 * @arg @ref LL_MPU_REGION_NUMBER10
633 * @arg @ref LL_MPU_REGION_NUMBER11
634 * @arg @ref LL_MPU_REGION_NUMBER12
635 * @arg @ref LL_MPU_REGION_NUMBER13
636 * @arg @ref LL_MPU_REGION_NUMBER14
637 * @arg @ref LL_MPU_REGION_NUMBER15
638 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
639 * @retval State of bit (1 or 0).
640 */
LL_MPU_IsEnabledRegion(uint32_t Region)641 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
642 {
643 /* Set region index */
644 WRITE_REG(MPU->RNR, Region);
645
646 /* Return MPU region status */
647 return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
648 }
649
650 #ifdef MPU_NS
651 /**
652 * @brief Enable a non-secure MPU region
653 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS
654 * @param Region This parameter can be one of the following values:
655 * @arg @ref LL_MPU_REGION_NUMBER0
656 * @arg @ref LL_MPU_REGION_NUMBER1
657 * @arg @ref LL_MPU_REGION_NUMBER2
658 * @arg @ref LL_MPU_REGION_NUMBER3
659 * @arg @ref LL_MPU_REGION_NUMBER4
660 * @arg @ref LL_MPU_REGION_NUMBER5
661 * @arg @ref LL_MPU_REGION_NUMBER6
662 * @arg @ref LL_MPU_REGION_NUMBER7
663 * @arg @ref LL_MPU_REGION_NUMBER8
664 * @arg @ref LL_MPU_REGION_NUMBER9
665 * @arg @ref LL_MPU_REGION_NUMBER10
666 * @arg @ref LL_MPU_REGION_NUMBER11
667 * @arg @ref LL_MPU_REGION_NUMBER12
668 * @arg @ref LL_MPU_REGION_NUMBER13
669 * @arg @ref LL_MPU_REGION_NUMBER14
670 * @arg @ref LL_MPU_REGION_NUMBER15
671 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
672 * @retval None
673 */
LL_MPU_EnableRegion_NS(uint32_t Region)674 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
675 {
676 /* Set Region number */
677 WRITE_REG(MPU_NS->RNR, Region);
678
679 /* Enable the MPU region */
680 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
681 }
682
683 /**
684 * @brief Check if non-secure MPU region is enabled or not
685 * @rmtoll MPU_RNR EN LL_MPU_IsEnabledRegion_NS
686 * @param Region This parameter can be one of the following values:
687 * @arg @ref LL_MPU_REGION_NUMBER0
688 * @arg @ref LL_MPU_REGION_NUMBER1
689 * @arg @ref LL_MPU_REGION_NUMBER2
690 * @arg @ref LL_MPU_REGION_NUMBER3
691 * @arg @ref LL_MPU_REGION_NUMBER4
692 * @arg @ref LL_MPU_REGION_NUMBER5
693 * @arg @ref LL_MPU_REGION_NUMBER6
694 * @arg @ref LL_MPU_REGION_NUMBER7
695 * @arg @ref LL_MPU_REGION_NUMBER8
696 * @arg @ref LL_MPU_REGION_NUMBER9
697 * @arg @ref LL_MPU_REGION_NUMBER10
698 * @arg @ref LL_MPU_REGION_NUMBER11
699 * @arg @ref LL_MPU_REGION_NUMBER12
700 * @arg @ref LL_MPU_REGION_NUMBER13
701 * @arg @ref LL_MPU_REGION_NUMBER14
702 * @arg @ref LL_MPU_REGION_NUMBER15
703 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
704 * @retval State of bit (1 or 0).
705 */
LL_MPU_IsEnabledRegion_NS(uint32_t Region)706 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
707 {
708 /* Set region index */
709 WRITE_REG(MPU_NS->RNR, Region);
710
711 /* Return non-secure MPU region status */
712 return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
713 }
714 #endif /* MPU_NS */
715
716 /**
717 * @brief Disable a MPU region
718 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
719 * MPU_RLAR EN LL_MPU_DisableRegion
720 * @param Region This parameter can be one of the following values:
721 * @arg @ref LL_MPU_REGION_NUMBER0
722 * @arg @ref LL_MPU_REGION_NUMBER1
723 * @arg @ref LL_MPU_REGION_NUMBER2
724 * @arg @ref LL_MPU_REGION_NUMBER3
725 * @arg @ref LL_MPU_REGION_NUMBER4
726 * @arg @ref LL_MPU_REGION_NUMBER5
727 * @arg @ref LL_MPU_REGION_NUMBER6
728 * @arg @ref LL_MPU_REGION_NUMBER7
729 * @arg @ref LL_MPU_REGION_NUMBER8
730 * @arg @ref LL_MPU_REGION_NUMBER9
731 * @arg @ref LL_MPU_REGION_NUMBER10
732 * @arg @ref LL_MPU_REGION_NUMBER11
733 * @arg @ref LL_MPU_REGION_NUMBER12
734 * @arg @ref LL_MPU_REGION_NUMBER13
735 * @arg @ref LL_MPU_REGION_NUMBER14
736 * @arg @ref LL_MPU_REGION_NUMBER15
737 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
738 * @retval None
739 */
LL_MPU_DisableRegion(uint32_t Region)740 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
741 {
742 /* Set Region number */
743 WRITE_REG(MPU->RNR, Region);
744
745 /* Disable the MPU region */
746 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
747 }
748
749 #ifdef MPU_NS
750 /**
751 * @brief Disable a non-secure MPU region
752 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
753 * MPU_RLAR EN LL_MPU_DisableRegion_NS
754 * @param Region This parameter can be one of the following values:
755 * @arg @ref LL_MPU_REGION_NUMBER0
756 * @arg @ref LL_MPU_REGION_NUMBER1
757 * @arg @ref LL_MPU_REGION_NUMBER2
758 * @arg @ref LL_MPU_REGION_NUMBER3
759 * @arg @ref LL_MPU_REGION_NUMBER4
760 * @arg @ref LL_MPU_REGION_NUMBER5
761 * @arg @ref LL_MPU_REGION_NUMBER6
762 * @arg @ref LL_MPU_REGION_NUMBER7
763 * @arg @ref LL_MPU_REGION_NUMBER8
764 * @arg @ref LL_MPU_REGION_NUMBER9
765 * @arg @ref LL_MPU_REGION_NUMBER10
766 * @arg @ref LL_MPU_REGION_NUMBER11
767 * @arg @ref LL_MPU_REGION_NUMBER12
768 * @arg @ref LL_MPU_REGION_NUMBER13
769 * @arg @ref LL_MPU_REGION_NUMBER14
770 * @arg @ref LL_MPU_REGION_NUMBER15
771 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
772 * @retval None
773 */
LL_MPU_DisableRegion_NS(uint32_t Region)774 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
775 {
776 /* Set Region number */
777 WRITE_REG(MPU_NS->RNR, Region);
778
779 /* Disable the MPU region */
780 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
781 }
782 #endif /* MPU_NS */
783
784 /**
785 * @brief Configure and enable a MPU region
786 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
787 * MPU_RBAR BASE LL_MPU_ConfigRegion\n
788 * MPU_RLAR LIMIT LL_MPU_ConfigRegion\n
789 * MPU_RBAR XN LL_MPU_ConfigRegion\n
790 * MPU_RBAR AP LL_MPU_ConfigRegion\n
791 * MPU_RBAR SH LL_MPU_ConfigRegion\n
792 * MPU_RLAR EN LL_MPU_ConfigRegion\n
793 * MPU_RLAR AttrX LL_MPU_ConfigRegion
794 * @param Region This parameter can be one of the following values:
795 * @arg @ref LL_MPU_REGION_NUMBER0
796 * @arg @ref LL_MPU_REGION_NUMBER1
797 * @arg @ref LL_MPU_REGION_NUMBER2
798 * @arg @ref LL_MPU_REGION_NUMBER3
799 * @arg @ref LL_MPU_REGION_NUMBER4
800 * @arg @ref LL_MPU_REGION_NUMBER5
801 * @arg @ref LL_MPU_REGION_NUMBER6
802 * @arg @ref LL_MPU_REGION_NUMBER7
803 * @arg @ref LL_MPU_REGION_NUMBER8
804 * @arg @ref LL_MPU_REGION_NUMBER9
805 * @arg @ref LL_MPU_REGION_NUMBER10
806 * @arg @ref LL_MPU_REGION_NUMBER11
807 * @arg @ref LL_MPU_REGION_NUMBER12
808 * @arg @ref LL_MPU_REGION_NUMBER13
809 * @arg @ref LL_MPU_REGION_NUMBER14
810 * @arg @ref LL_MPU_REGION_NUMBER15
811 * @param Attributes This parameter can be a combination of the following values:
812 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
813 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
814 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
815 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
816 * or @ref LL_MPU_REGION_ALL_RO
817 * @param AttrIndx This parameter can be one of the following values:
818 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
819 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
820 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
821 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
822 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
823 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
824 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
825 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
826 * @param BaseAddress Value of region base address
827 * @param LimitAddress Value of region limit address
828 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
829 * @retval None
830 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)831 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
832 uint32_t LimitAddress)
833 {
834 /* Set region index */
835 WRITE_REG(MPU->RNR, Region);
836
837 /* Set region base address and region access attributes */
838 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
839
840 /* Set region limit address, memory attributes index and enable region */
841 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
842 }
843
844 #ifdef MPU_NS
845 /**
846 * @brief Configure and enable a non-secure MPU region
847 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
848 * MPU_RBAR BASE LL_MPU_ConfigRegion_NS\n
849 * MPU_RLAR LIMIT LL_MPU_ConfigRegion_NS\n
850 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
851 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
852 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
853 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
854 * MPU_RLAR AttrX LL_MPU_ConfigRegion_NS
855 * @param Region This parameter can be one of the following values:
856 * @arg @ref LL_MPU_REGION_NUMBER0
857 * @arg @ref LL_MPU_REGION_NUMBER1
858 * @arg @ref LL_MPU_REGION_NUMBER2
859 * @arg @ref LL_MPU_REGION_NUMBER3
860 * @arg @ref LL_MPU_REGION_NUMBER4
861 * @arg @ref LL_MPU_REGION_NUMBER5
862 * @arg @ref LL_MPU_REGION_NUMBER6
863 * @arg @ref LL_MPU_REGION_NUMBER7
864 * @arg @ref LL_MPU_REGION_NUMBER8
865 * @arg @ref LL_MPU_REGION_NUMBER9
866 * @arg @ref LL_MPU_REGION_NUMBER10
867 * @arg @ref LL_MPU_REGION_NUMBER11
868 * @arg @ref LL_MPU_REGION_NUMBER12
869 * @arg @ref LL_MPU_REGION_NUMBER13
870 * @arg @ref LL_MPU_REGION_NUMBER14
871 * @arg @ref LL_MPU_REGION_NUMBER15
872 * @param Attributes This parameter can be a combination of the following values:
873 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
874 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
875 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
876 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
877 * or @ref LL_MPU_REGION_ALL_RO
878 * @param AttrIndx This parameter can be one of the following values:
879 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
880 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
881 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
882 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
883 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
884 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
885 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
886 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
887 * @param BaseAddress Value of region base address
888 * @param LimitAddress Value of region limit address
889 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
890 * @retval None
891 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)892 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
893 uint32_t BaseAddress, uint32_t LimitAddress)
894 {
895 /* Set Region number */
896 WRITE_REG(MPU_NS->RNR, Region);
897
898 /* Set region base address and region access attributes */
899 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
900
901 /* Set region limit address, memory attributes index and enable region */
902 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
903 }
904 #endif /* MPU_NS */
905
906 /**
907 * @brief Configure a MPU region address range
908 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
909 * MPU_RBAR BASE LL_MPU_ConfigRegionAddress\n
910 * MPU_RLAR LIMIT LL_MPU_ConfigRegionAddress
911 * @param Region This parameter can be one of the following values:
912 * @arg @ref LL_MPU_REGION_NUMBER0
913 * @arg @ref LL_MPU_REGION_NUMBER1
914 * @arg @ref LL_MPU_REGION_NUMBER2
915 * @arg @ref LL_MPU_REGION_NUMBER3
916 * @arg @ref LL_MPU_REGION_NUMBER4
917 * @arg @ref LL_MPU_REGION_NUMBER5
918 * @arg @ref LL_MPU_REGION_NUMBER6
919 * @arg @ref LL_MPU_REGION_NUMBER7
920 * @arg @ref LL_MPU_REGION_NUMBER8
921 * @arg @ref LL_MPU_REGION_NUMBER9
922 * @arg @ref LL_MPU_REGION_NUMBER10
923 * @arg @ref LL_MPU_REGION_NUMBER11
924 * @arg @ref LL_MPU_REGION_NUMBER12
925 * @arg @ref LL_MPU_REGION_NUMBER13
926 * @arg @ref LL_MPU_REGION_NUMBER14
927 * @arg @ref LL_MPU_REGION_NUMBER15
928 * @param BaseAddress Value of region base address
929 * @param LimitAddress Value of region limit address
930 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
931 * @retval None
932 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)933 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
934 {
935 /* Set Region number */
936 WRITE_REG(MPU->RNR, Region);
937
938 /* Modify region base address */
939 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
940
941 /* Modify region limit address */
942 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
943 }
944
945 #ifdef MPU_NS
946 /**
947 * @brief Configure a non-secure MPU region address range
948 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
949 * MPU_RBAR BASE LL_MPU_ConfigRegionAddress_NS\n
950 * MPU_RLAR LIMIT LL_MPU_ConfigRegionAddress_NS
951 * @param Region This parameter can be one of the following values:
952 * @arg @ref LL_MPU_REGION_NUMBER0
953 * @arg @ref LL_MPU_REGION_NUMBER1
954 * @arg @ref LL_MPU_REGION_NUMBER2
955 * @arg @ref LL_MPU_REGION_NUMBER3
956 * @arg @ref LL_MPU_REGION_NUMBER4
957 * @arg @ref LL_MPU_REGION_NUMBER5
958 * @arg @ref LL_MPU_REGION_NUMBER6
959 * @arg @ref LL_MPU_REGION_NUMBER7
960 * @arg @ref LL_MPU_REGION_NUMBER8
961 * @arg @ref LL_MPU_REGION_NUMBER9
962 * @arg @ref LL_MPU_REGION_NUMBER10
963 * @arg @ref LL_MPU_REGION_NUMBER11
964 * @arg @ref LL_MPU_REGION_NUMBER12
965 * @arg @ref LL_MPU_REGION_NUMBER13
966 * @arg @ref LL_MPU_REGION_NUMBER14
967 * @arg @ref LL_MPU_REGION_NUMBER15
968 * @param BaseAddress Value of region base address
969 * @param LimitAddress Value of region limit address
970 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
971 * @retval None
972 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)973 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
974 {
975 /* Set Region number */
976 WRITE_REG(MPU_NS->RNR, Region);
977
978 /* Set base address */
979 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
980
981 /* Set limit address */
982 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
983 }
984 #endif /* MPU_NS */
985
986 /**
987 * @brief Configure a MPU attributes index
988 * @rmtoll MPU_MAIR0 AttrX LL_MPU_ConfigAttributes\n
989 * MPU_MAIR1 AttrX LL_MPU_ConfigAttributes
990 * @param AttIndex This parameter can be one of the following values:
991 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
992 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
993 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
994 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
995 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
996 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
997 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
998 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
999 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
1000 * @retval None
1001 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)1002 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
1003 {
1004 /* When selected index is in range [0;3] */
1005 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1006 {
1007 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
1008 MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1009 }
1010 /* When selected index is in range [4;7] */
1011 else
1012 {
1013 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
1014 MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1015 }
1016 }
1017
1018 #ifdef MPU_NS
1019 /**
1020 * @brief Configure a non-secure MPU attributes index
1021 * @rmtoll MPU_MAIR0 AttrX LL_MPU_ConfigAttributes_NS\n
1022 * MPU_MAIR1 AttrX LL_MPU_ConfigAttributes_NS
1023 * @param AttIndex This parameter can be one of the following values:
1024 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1025 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1026 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1027 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1028 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1029 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1030 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1031 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1032 * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
1033 * @retval None
1034 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)1035 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1036 {
1037 /* When selected index is in range [0;3] */
1038 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1039 {
1040 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
1041 MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1042 }
1043 /* When selected index is in range [4;7] */
1044 else
1045 {
1046 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
1047 MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1048 }
1049 }
1050 #endif /* MPU_NS */
1051
1052 /**
1053 * @brief Configure a MPU region limit address
1054 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
1055 * MPU_RLAR LIMIT LL_MPU_SetRegionLimitAddress
1056 * @param Region This parameter can be one of the following values:
1057 * @arg @ref LL_MPU_REGION_NUMBER0
1058 * @arg @ref LL_MPU_REGION_NUMBER1
1059 * @arg @ref LL_MPU_REGION_NUMBER2
1060 * @arg @ref LL_MPU_REGION_NUMBER3
1061 * @arg @ref LL_MPU_REGION_NUMBER4
1062 * @arg @ref LL_MPU_REGION_NUMBER5
1063 * @arg @ref LL_MPU_REGION_NUMBER6
1064 * @arg @ref LL_MPU_REGION_NUMBER7
1065 * @arg @ref LL_MPU_REGION_NUMBER8
1066 * @arg @ref LL_MPU_REGION_NUMBER9
1067 * @arg @ref LL_MPU_REGION_NUMBER10
1068 * @arg @ref LL_MPU_REGION_NUMBER11
1069 * @arg @ref LL_MPU_REGION_NUMBER12
1070 * @arg @ref LL_MPU_REGION_NUMBER13
1071 * @arg @ref LL_MPU_REGION_NUMBER14
1072 * @arg @ref LL_MPU_REGION_NUMBER15
1073 * @param LimitAddress Value of region limit address
1074 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1075 * @retval None
1076 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)1077 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
1078 {
1079 /* Set Region number */
1080 WRITE_REG(MPU->RNR, Region);
1081
1082 /* Set limit address */
1083 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1084 }
1085
1086 /**
1087 * @brief Get a MPU region limit address
1088 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
1089 * MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress
1090 * @param Region This parameter can be one of the following values:
1091 * @arg @ref LL_MPU_REGION_NUMBER0
1092 * @arg @ref LL_MPU_REGION_NUMBER1
1093 * @arg @ref LL_MPU_REGION_NUMBER2
1094 * @arg @ref LL_MPU_REGION_NUMBER3
1095 * @arg @ref LL_MPU_REGION_NUMBER4
1096 * @arg @ref LL_MPU_REGION_NUMBER5
1097 * @arg @ref LL_MPU_REGION_NUMBER6
1098 * @arg @ref LL_MPU_REGION_NUMBER7
1099 * @arg @ref LL_MPU_REGION_NUMBER8
1100 * @arg @ref LL_MPU_REGION_NUMBER9
1101 * @arg @ref LL_MPU_REGION_NUMBER10
1102 * @arg @ref LL_MPU_REGION_NUMBER11
1103 * @arg @ref LL_MPU_REGION_NUMBER12
1104 * @arg @ref LL_MPU_REGION_NUMBER13
1105 * @arg @ref LL_MPU_REGION_NUMBER14
1106 * @arg @ref LL_MPU_REGION_NUMBER15
1107 * @retval MPU region limit address
1108 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)1109 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
1110 {
1111 /* Set Region number */
1112 WRITE_REG(MPU->RNR, Region);
1113
1114 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
1115 }
1116
1117 /**
1118 * @brief Configure a MPU region base address
1119 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
1120 * MPU_RBAR BASE LL_MPU_SetRegionBaseAddress
1121 * @param Region This parameter can be one of the following values:
1122 * @arg @ref LL_MPU_REGION_NUMBER0
1123 * @arg @ref LL_MPU_REGION_NUMBER1
1124 * @arg @ref LL_MPU_REGION_NUMBER2
1125 * @arg @ref LL_MPU_REGION_NUMBER3
1126 * @arg @ref LL_MPU_REGION_NUMBER4
1127 * @arg @ref LL_MPU_REGION_NUMBER5
1128 * @arg @ref LL_MPU_REGION_NUMBER6
1129 * @arg @ref LL_MPU_REGION_NUMBER7
1130 * @arg @ref LL_MPU_REGION_NUMBER8
1131 * @arg @ref LL_MPU_REGION_NUMBER9
1132 * @arg @ref LL_MPU_REGION_NUMBER10
1133 * @arg @ref LL_MPU_REGION_NUMBER11
1134 * @arg @ref LL_MPU_REGION_NUMBER12
1135 * @arg @ref LL_MPU_REGION_NUMBER13
1136 * @arg @ref LL_MPU_REGION_NUMBER14
1137 * @arg @ref LL_MPU_REGION_NUMBER15
1138 * @param BaseAddress Value of region base address
1139 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1140 * @retval None
1141 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)1142 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
1143 {
1144 /* Set Region number */
1145 WRITE_REG(MPU->RNR, Region);
1146
1147 /* Set base address */
1148 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1149 }
1150
1151 /**
1152 * @brief Get a MPU region base address
1153 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
1154 * MPU_RBAR BASE LL_MPU_GetRegionBaseAddress
1155 * @param Region This parameter can be one of the following values:
1156 * @arg @ref LL_MPU_REGION_NUMBER0
1157 * @arg @ref LL_MPU_REGION_NUMBER1
1158 * @arg @ref LL_MPU_REGION_NUMBER2
1159 * @arg @ref LL_MPU_REGION_NUMBER3
1160 * @arg @ref LL_MPU_REGION_NUMBER4
1161 * @arg @ref LL_MPU_REGION_NUMBER5
1162 * @arg @ref LL_MPU_REGION_NUMBER6
1163 * @arg @ref LL_MPU_REGION_NUMBER7
1164 * @arg @ref LL_MPU_REGION_NUMBER8
1165 * @arg @ref LL_MPU_REGION_NUMBER9
1166 * @arg @ref LL_MPU_REGION_NUMBER10
1167 * @arg @ref LL_MPU_REGION_NUMBER11
1168 * @arg @ref LL_MPU_REGION_NUMBER12
1169 * @arg @ref LL_MPU_REGION_NUMBER13
1170 * @arg @ref LL_MPU_REGION_NUMBER14
1171 * @arg @ref LL_MPU_REGION_NUMBER15
1172 * @retval MPU region base address
1173 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)1174 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
1175 {
1176 /* Set Region number */
1177 WRITE_REG(MPU->RNR, Region);
1178
1179 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
1180 }
1181
1182 /**
1183 * @brief Configure a MPU region access attributes and enable a region
1184 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
1185 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
1186 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
1187 * MPU_RBAR SH LL_MPU_SetRegionAccess
1188 * @param Region This parameter can be one of the following values:
1189 * @arg @ref LL_MPU_REGION_NUMBER0
1190 * @arg @ref LL_MPU_REGION_NUMBER1
1191 * @arg @ref LL_MPU_REGION_NUMBER2
1192 * @arg @ref LL_MPU_REGION_NUMBER3
1193 * @arg @ref LL_MPU_REGION_NUMBER4
1194 * @arg @ref LL_MPU_REGION_NUMBER5
1195 * @arg @ref LL_MPU_REGION_NUMBER6
1196 * @arg @ref LL_MPU_REGION_NUMBER7
1197 * @arg @ref LL_MPU_REGION_NUMBER8
1198 * @arg @ref LL_MPU_REGION_NUMBER9
1199 * @arg @ref LL_MPU_REGION_NUMBER10
1200 * @arg @ref LL_MPU_REGION_NUMBER11
1201 * @arg @ref LL_MPU_REGION_NUMBER12
1202 * @arg @ref LL_MPU_REGION_NUMBER13
1203 * @arg @ref LL_MPU_REGION_NUMBER14
1204 * @arg @ref LL_MPU_REGION_NUMBER15
1205 * @param Attributes This parameter can be a combination of the following values:
1206 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1207 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1208 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1209 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1210 * or @ref LL_MPU_REGION_ALL_RO
1211 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1212 * @retval None
1213 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)1214 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
1215 {
1216 /* Set Region number */
1217 WRITE_REG(MPU->RNR, Region);
1218
1219 /* Set base address */
1220 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1221 }
1222
1223 /**
1224 * @brief Get a MPU region access attributes
1225 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
1226 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
1227 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
1228 * MPU_RBAR SH LL_MPU_GetRegionAccess
1229 * @param Region This parameter can be one of the following values:
1230 * @arg @ref LL_MPU_REGION_NUMBER0
1231 * @arg @ref LL_MPU_REGION_NUMBER1
1232 * @arg @ref LL_MPU_REGION_NUMBER2
1233 * @arg @ref LL_MPU_REGION_NUMBER3
1234 * @arg @ref LL_MPU_REGION_NUMBER4
1235 * @arg @ref LL_MPU_REGION_NUMBER5
1236 * @arg @ref LL_MPU_REGION_NUMBER6
1237 * @arg @ref LL_MPU_REGION_NUMBER7
1238 * @arg @ref LL_MPU_REGION_NUMBER8
1239 * @arg @ref LL_MPU_REGION_NUMBER9
1240 * @arg @ref LL_MPU_REGION_NUMBER10
1241 * @arg @ref LL_MPU_REGION_NUMBER11
1242 * @arg @ref LL_MPU_REGION_NUMBER12
1243 * @arg @ref LL_MPU_REGION_NUMBER13
1244 * @arg @ref LL_MPU_REGION_NUMBER14
1245 * @arg @ref LL_MPU_REGION_NUMBER15
1246 * @retval MPU region access attributes
1247 */
LL_MPU_GetRegionAccess(uint32_t Region)1248 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
1249 {
1250 /* Set Region number */
1251 WRITE_REG(MPU->RNR, Region);
1252
1253 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1254 }
1255
1256 #ifdef MPU_NS
1257 /**
1258 * @brief Configure a non-secure MPU region limit address
1259 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1260 * MPU_RLAR LIMIT LL_MPU_SetRegionLimitAddress_NS
1261 * @param Region This parameter can be one of the following values:
1262 * @arg @ref LL_MPU_REGION_NUMBER0
1263 * @arg @ref LL_MPU_REGION_NUMBER1
1264 * @arg @ref LL_MPU_REGION_NUMBER2
1265 * @arg @ref LL_MPU_REGION_NUMBER3
1266 * @arg @ref LL_MPU_REGION_NUMBER4
1267 * @arg @ref LL_MPU_REGION_NUMBER5
1268 * @arg @ref LL_MPU_REGION_NUMBER6
1269 * @arg @ref LL_MPU_REGION_NUMBER7
1270 * @arg @ref LL_MPU_REGION_NUMBER8
1271 * @arg @ref LL_MPU_REGION_NUMBER9
1272 * @arg @ref LL_MPU_REGION_NUMBER10
1273 * @arg @ref LL_MPU_REGION_NUMBER11
1274 * @arg @ref LL_MPU_REGION_NUMBER12
1275 * @arg @ref LL_MPU_REGION_NUMBER13
1276 * @arg @ref LL_MPU_REGION_NUMBER14
1277 * @arg @ref LL_MPU_REGION_NUMBER15
1278 * @param LimitAddress Value of region limit address
1279 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1280 * @retval None
1281 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1282 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1283 {
1284 /* Set Region number */
1285 WRITE_REG(MPU_NS->RNR, Region);
1286
1287 /* Set limit address */
1288 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1289 }
1290
1291 /**
1292 * @brief Get a non-secure MPU region limit address
1293 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1294 * MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS
1295 * @param Region This parameter can be one of the following values:
1296 * @arg @ref LL_MPU_REGION_NUMBER0
1297 * @arg @ref LL_MPU_REGION_NUMBER1
1298 * @arg @ref LL_MPU_REGION_NUMBER2
1299 * @arg @ref LL_MPU_REGION_NUMBER3
1300 * @arg @ref LL_MPU_REGION_NUMBER4
1301 * @arg @ref LL_MPU_REGION_NUMBER5
1302 * @arg @ref LL_MPU_REGION_NUMBER6
1303 * @arg @ref LL_MPU_REGION_NUMBER7
1304 * @arg @ref LL_MPU_REGION_NUMBER8
1305 * @arg @ref LL_MPU_REGION_NUMBER9
1306 * @arg @ref LL_MPU_REGION_NUMBER10
1307 * @arg @ref LL_MPU_REGION_NUMBER11
1308 * @arg @ref LL_MPU_REGION_NUMBER12
1309 * @arg @ref LL_MPU_REGION_NUMBER13
1310 * @arg @ref LL_MPU_REGION_NUMBER14
1311 * @arg @ref LL_MPU_REGION_NUMBER15
1312 * @retval Non-secure MPU region limit address
1313 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1314 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1315 {
1316 /* Set Region number */
1317 WRITE_REG(MPU_NS->RNR, Region);
1318
1319 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1320 }
1321
1322 /**
1323 * @brief Configure a non-secure MPU region base address
1324 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1325 * MPU_RBAR BASE LL_MPU_SetRegionBaseAddress_NS
1326 * @param Region This parameter can be one of the following values:
1327 * @arg @ref LL_MPU_REGION_NUMBER0
1328 * @arg @ref LL_MPU_REGION_NUMBER1
1329 * @arg @ref LL_MPU_REGION_NUMBER2
1330 * @arg @ref LL_MPU_REGION_NUMBER3
1331 * @arg @ref LL_MPU_REGION_NUMBER4
1332 * @arg @ref LL_MPU_REGION_NUMBER5
1333 * @arg @ref LL_MPU_REGION_NUMBER6
1334 * @arg @ref LL_MPU_REGION_NUMBER7
1335 * @arg @ref LL_MPU_REGION_NUMBER8
1336 * @arg @ref LL_MPU_REGION_NUMBER9
1337 * @arg @ref LL_MPU_REGION_NUMBER10
1338 * @arg @ref LL_MPU_REGION_NUMBER11
1339 * @arg @ref LL_MPU_REGION_NUMBER12
1340 * @arg @ref LL_MPU_REGION_NUMBER13
1341 * @arg @ref LL_MPU_REGION_NUMBER14
1342 * @arg @ref LL_MPU_REGION_NUMBER15
1343 * @param BaseAddress Value of region base address
1344 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1345 * @retval None
1346 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1347 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1348 {
1349 /* Set Region number */
1350 WRITE_REG(MPU_NS->RNR, Region);
1351
1352 /* Set base address */
1353 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1354 }
1355
1356 /**
1357 * @brief Get a non-secure MPU region base address
1358 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1359 * MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS
1360 * @param Region This parameter can be one of the following values:
1361 * @arg @ref LL_MPU_REGION_NUMBER0
1362 * @arg @ref LL_MPU_REGION_NUMBER1
1363 * @arg @ref LL_MPU_REGION_NUMBER2
1364 * @arg @ref LL_MPU_REGION_NUMBER3
1365 * @arg @ref LL_MPU_REGION_NUMBER4
1366 * @arg @ref LL_MPU_REGION_NUMBER5
1367 * @arg @ref LL_MPU_REGION_NUMBER6
1368 * @arg @ref LL_MPU_REGION_NUMBER7
1369 * @arg @ref LL_MPU_REGION_NUMBER8
1370 * @arg @ref LL_MPU_REGION_NUMBER9
1371 * @arg @ref LL_MPU_REGION_NUMBER10
1372 * @arg @ref LL_MPU_REGION_NUMBER11
1373 * @arg @ref LL_MPU_REGION_NUMBER12
1374 * @arg @ref LL_MPU_REGION_NUMBER13
1375 * @arg @ref LL_MPU_REGION_NUMBER14
1376 * @arg @ref LL_MPU_REGION_NUMBER15
1377 * @retval Non-secure MPU region base address
1378 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1379 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1380 {
1381 /* Set Region number */
1382 WRITE_REG(MPU_NS->RNR, Region);
1383
1384 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1385 }
1386
1387 /**
1388 * @brief Configure a non-secure MPU region access attributes and enable a region
1389 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1390 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1391 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1392 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS
1393 * @param Region This parameter can be one of the following values:
1394 * @arg @ref LL_MPU_REGION_NUMBER0
1395 * @arg @ref LL_MPU_REGION_NUMBER1
1396 * @arg @ref LL_MPU_REGION_NUMBER2
1397 * @arg @ref LL_MPU_REGION_NUMBER3
1398 * @arg @ref LL_MPU_REGION_NUMBER4
1399 * @arg @ref LL_MPU_REGION_NUMBER5
1400 * @arg @ref LL_MPU_REGION_NUMBER6
1401 * @arg @ref LL_MPU_REGION_NUMBER7
1402 * @arg @ref LL_MPU_REGION_NUMBER8
1403 * @arg @ref LL_MPU_REGION_NUMBER9
1404 * @arg @ref LL_MPU_REGION_NUMBER10
1405 * @arg @ref LL_MPU_REGION_NUMBER11
1406 * @arg @ref LL_MPU_REGION_NUMBER12
1407 * @arg @ref LL_MPU_REGION_NUMBER13
1408 * @arg @ref LL_MPU_REGION_NUMBER14
1409 * @arg @ref LL_MPU_REGION_NUMBER15
1410 * @param Attributes This parameter can be a combination of the following values:
1411 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1412 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1413 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1414 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1415 * or @ref LL_MPU_REGION_ALL_RO
1416 * @note Cortex-M55 supports 16 secure and 16 non secure regions.
1417 * @retval None
1418 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1419 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1420 {
1421 /* Set Region number */
1422 WRITE_REG(MPU_NS->RNR, Region);
1423
1424 /* Set base address Attributes */
1425 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1426 }
1427
1428 /**
1429 * @brief Get a non-secure MPU region access attributes
1430 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1431 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1432 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1433 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS
1434 * @param Region This parameter can be one of the following values:
1435 * @arg @ref LL_MPU_REGION_NUMBER0
1436 * @arg @ref LL_MPU_REGION_NUMBER1
1437 * @arg @ref LL_MPU_REGION_NUMBER2
1438 * @arg @ref LL_MPU_REGION_NUMBER3
1439 * @arg @ref LL_MPU_REGION_NUMBER4
1440 * @arg @ref LL_MPU_REGION_NUMBER5
1441 * @arg @ref LL_MPU_REGION_NUMBER6
1442 * @arg @ref LL_MPU_REGION_NUMBER7
1443 * @arg @ref LL_MPU_REGION_NUMBER8
1444 * @arg @ref LL_MPU_REGION_NUMBER9
1445 * @arg @ref LL_MPU_REGION_NUMBER10
1446 * @arg @ref LL_MPU_REGION_NUMBER11
1447 * @arg @ref LL_MPU_REGION_NUMBER12
1448 * @arg @ref LL_MPU_REGION_NUMBER13
1449 * @arg @ref LL_MPU_REGION_NUMBER14
1450 * @arg @ref LL_MPU_REGION_NUMBER15
1451 * @retval Non-secure MPU region access attributes
1452 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1453 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1454 {
1455 /* Set Region number */
1456 WRITE_REG(MPU_NS->RNR, Region);
1457
1458 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1459 }
1460 #endif /* MPU_NS */
1461
1462 /**
1463 * @}
1464 */
1465
1466 /**
1467 * @}
1468 */
1469
1470 /**
1471 * @}
1472 */
1473
1474 /**
1475 * @}
1476 */
1477
1478 #ifdef __cplusplus
1479 }
1480 #endif
1481
1482 #endif /* STM32N6xx_LL_CORTEX_H */
1483
