/hal_stm32-latest/stm32cube/stm32g0xx/soc/ |
D | stm32g071xx.h | 8707 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 8708 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset d…
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D | stm32g081xx.h | 9011 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 9012 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset d…
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D | stm32g0c1xx.h | 10601 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 10602 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset d…
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D | stm32g0b1xx.h | 10297 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 10298 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset d…
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/hal_stm32-latest/stm32cube/stm32g4xx/soc/ |
D | stm32g441xx.h | 12633 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 12634 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32gbk1cb.h | 12350 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 12351 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g431xx.h | 12403 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 12404 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g4a1xx.h | 13143 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 13144 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g491xx.h | 12913 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 12914 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g473xx.h | 13704 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 13705 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g471xx.h | 13136 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 13137 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g483xx.h | 13934 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 13935 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g474xx.h | 17283 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 17284 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32g484xx.h | 17513 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 17514 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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/hal_stm32-latest/stm32cube/stm32l5xx/soc/ |
D | stm32l552xx.h | 17972 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 17973 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32l562xx.h | 18743 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 18744 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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/hal_stm32-latest/stm32cube/stm32h5xx/soc/ |
D | stm32h523xx.h | 16898 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 16899 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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D | stm32h562xx.h | 18442 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 18443 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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D | stm32h533xx.h | 17491 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 17492 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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D | stm32h573xx.h | 21167 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 21168 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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D | stm32h563xx.h | 20574 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 20575 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/ |
D | stm32h7r3xx.h | 20658 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 20659 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32h7s7xx.h | 21973 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 21974 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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D | stm32h7s3xx.h | 21541 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ macro 21542 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset di…
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/hal_stm32-latest/stm32cube/stm32u5xx/soc/ |
D | stm32u575xx.h | 20754 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010… macro 20755 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset…
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