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Searched refs:TIM1_OR2_ETRSEL_1 (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_tim_ex.h97 #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /*!< TIM1…
Dstm32l5xx_ll_tim.h998 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< ETR inp…
999 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_OR2_ETRSEL_1 | TIM1_OR2_ETRSEL_0) /*!< ETR inp…
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_tim_ex.h104 #define TIM_TIM1_ETR_COMP2 TIM1_OR2_ETRSEL_1 /*!< TIM1…
Dstm32l4xx_ll_tim.h986 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*…
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h8751 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l412xx.h8526 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l433xx.h13232 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l451xx.h13340 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l442xx.h12398 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l431xx.h13003 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l432xx.h12173 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l443xx.h13457 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l471xx.h14358 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l452xx.h13418 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l462xx.h13643 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l475xx.h14522 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l476xx.h14679 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l486xx.h14898 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l485xx.h14747 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l4a6xx.h16229 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l496xx.h15889 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l4r5xx.h16363 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l4r7xx.h16862 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
Dstm32l4s5xx.h16710 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h14877 #define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ macro

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