Searched refs:TIM1_AF1_ETRSEL_1 (Results 1 – 25 of 120) sorted by relevance
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112 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!…114 #define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…118 #define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!…119 #define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!…123 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…124 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…128 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!…134 #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!…136 #define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…140 #define TIM_TIM2_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!…[all …]
1043 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1045 #define LL_TIM_TIM1_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1049 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) …1050 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0…1054 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1055 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1059 …TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 …1071 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1073 #define LL_TIM_TIM2_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1077 #define LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) …[all …]
109 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< E…110 #define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< E…116 #define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< E…119 #define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< E…123 #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< A…125 #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< A…132 #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< E…133 #define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< E…139 #define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< E…142 #define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/*!< E…[all …]
1033 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1034 #define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1040 #define LL_TIM_TIM1_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) …1043 #define LL_TIM_TIM1_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1047 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1049 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1062 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1063 #define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1069 #define LL_TIM_TIM2_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) …1072 #define LL_TIM_TIM2_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL…[all …]
114 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!…116 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…127 #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…134 #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…137 #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…146 #define TIM_TIM2_ETR_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!…157 #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!…160 #define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!…166 #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!…169 #define TIM_TIM3_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!…[all …]
1050 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1052 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1067 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1069 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1076 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …1079 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…1088 …TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR in…1105 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …1108 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …1114 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) …[all …]
91 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is co…93 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is co…97 #define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is co…107 #define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is co…
999 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR inp…1002 #define LL_TIM_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR inp…1004 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR inp…1007 #define LL_TIM_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR inp…
93 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< T…94 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< T…97 #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< T…98 #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< T…
993 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 …994 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) …997 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) …998 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_…
932 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ET…935 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ET…936 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_A…940 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ET…943 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ET…944 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_A…948 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ET…951 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ET…954 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ET…960 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 …[all …]
91 #define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< …94 #define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< …95 #define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< …
93 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1…
459 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< OCREF_CLR_INT is connected to …
988 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*…
98 #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1…
458 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< OCREF_CLR_INT is connected to …
1000 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*…
6448 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
6509 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
6648 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
6712 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
7016 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
7111 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
7415 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ macro
