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Searched refs:SVMCR2 (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_pwr.h754 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in LL_PWR_EnableVddIO5()
764 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in LL_PWR_DisableVddIO5()
774 return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV) == (PWR_SVMCR2_VDDIO5SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO5()
934 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in LL_PWR_EnableVddIO5Monitoring()
944 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in LL_PWR_DisableVddIO5Monitoring()
954 return ((READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN) == (PWR_SVMCR2_VDDIO5VMEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO5Monitoring()
1142 MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, (VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos)); in LL_PWR_SetVddIO5VoltageRange()
1154 return (uint32_t)(READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos); in LL_PWR_GetVddIO5VoltageRange()
1194 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in LL_PWR_EnableVddIO5VoltageRangeSB()
1204 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in LL_PWR_DisableVddIO5VoltageRangeSB()
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Dstm32n6xx_hal_pwr.h348 …((__FLAG__) == PWR_FLAG_VDDIO5RDY) ? ((PWR->SVMCR2 & PWR_SVMCR2_VDDIO5RDY) == PWR_SVMCR2_VDDIO5RDY…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_pwr_ex.c896 MODIFY_REG(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL, VoltageRange << PWR_SVMCR2_VDDIO5VRSEL_Pos); in HAL_PWREx_ConfigVddIORange()
943 voltage_range = (READ_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSEL) >> PWR_SVMCR2_VDDIO5VRSEL_Pos); in HAL_PWREx_GetVddIORange()
988 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in HAL_PWREx_EnableVddIO5RangeSTBY()
997 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VRSTBY); in HAL_PWREx_DisableVddIO5RangeSTBY()
1084 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in HAL_PWREx_EnableVddIO5()
1093 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5SV); in HAL_PWREx_DisableVddIO5()
1193 SET_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in HAL_PWREx_EnableVddIO5VMEN()
1202 CLEAR_BIT(PWR->SVMCR2, PWR_SVMCR2_VDDIO5VMEN); in HAL_PWREx_DisableVddIO5VMEN()
Dstm32n6xx_ll_pwr.c67 WRITE_REG(PWR->SVMCR2, 0x00000000U); in LL_PWR_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h1868 …__IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offse… member
Dstm32n657xx.h1994 …__IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offse… member
Dstm32n655xx.h1966 …__IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offse… member
Dstm32n647xx.h1896 …__IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offse… member