1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_PWR_H 21 #define STM32N6xx_HAL_PWR_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup PWR 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup PWR_Exported_Types PWR Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief PWR PVD configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 50 This parameter can be a value of @ref PWR_PVD_Mode. */ 51 } PWR_PVDTypeDef; 52 /** 53 * @} 54 */ 55 56 /* Exported constants --------------------------------------------------------*/ 57 58 /** @defgroup PWR_Exported_Constants PWR Exported Constants 59 * @{ 60 */ 61 62 /** @defgroup PWR_PVD_Mode PWR PVD Mode 63 * @{ 64 */ 65 #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 66 #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ 67 #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ 68 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ 69 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 70 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 71 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 72 /** 73 * @} 74 */ 75 76 /** @defgroup PWR_Regulator_state_in_LP_mode PWR Regulator state in SLEEP/STOP mode 77 * @{ 78 */ 79 /* define for interface compatibility purpose */ 80 #define PWR_MAINREGULATOR_ON (0U) 81 /** 82 * @} 83 */ 84 85 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 86 * @{ 87 */ 88 #define PWR_SLEEPENTRY_WFI (1U) /*!< Wait For Interruption instruction to enter Sleep mode */ 89 #define PWR_SLEEPENTRY_WFE (2U) /*!< Wait For Event instruction to enter Sleep mode */ 90 #define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (3U) /*!< Wait For Event instruction to enter Sleep mode with no event clear */ 91 /** 92 * @} 93 */ 94 95 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 96 * @{ 97 */ 98 #define PWR_STOPENTRY_WFI (1U) /*!< Wait For Interruption instruction to enter Stop mode */ 99 #define PWR_STOPENTRY_WFE (2U) /*!< Wait For Event instruction to enter Stop mode */ 100 #define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (3U) /*!< Wait For Event instruction to enter Stop mode with no event clear */ 101 /** 102 * @} 103 */ 104 105 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask 106 * @{ 107 */ 108 #define PWR_EWUP_MASK (0x00FF0F0FU) 109 /** 110 * @} 111 */ 112 113 /** @defgroup PWR_WakeUp_Pins PWR Wake-Up Pins 114 * @{ 115 */ 116 /* High level and No pull (default configuration) */ 117 #define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 1 (with high level polarity) */ 118 #define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 2 (with high level polarity) */ 119 #define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 3 (with high level polarity) */ 120 #define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 4 (with high level polarity) */ 121 122 /* High level and No pull */ 123 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 /*!< Wakeup pin 1 (with high level polarity) */ 124 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 /*!< Wakeup pin 2 (with high level polarity) */ 125 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 /*!< Wakeup pin 3 (with high level polarity) */ 126 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 /*!< Wakeup pin 4 (with high level polarity) */ 127 128 /* Low level and No pull */ 129 #define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) /*!< Wakeup pin 1 (with low level polarity) */ 130 #define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) /*!< Wakeup pin 2 (with low level polarity) */ 131 #define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) /*!< Wakeup pin 3 (with low level polarity) */ 132 #define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) /*!< Wakeup pin 4 (with low level polarity) */ 133 /** 134 * @} 135 */ 136 137 /** @defgroup PWR_Flag_WUP PWR Flag WakeUp 138 * @{ 139 */ 140 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 141 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 142 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 143 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 144 #define PWR_FLAG_WKUP (PWR_FLAG_WKUP1 | PWR_WKUPCR_WKUPC2 | \ 145 PWR_FLAG_WKUP3 | PWR_WKUPCR_WKUPC4) 146 /** 147 * @} 148 */ 149 150 /** @defgroup PWR_PIN_Polarity PWR Pin Polarity configuration 151 * @{ 152 */ 153 #define PWR_PIN_POLARITY_HIGH (0x0U) 154 #define PWR_PIN_POLARITY_LOW (0x1U) 155 /** 156 * @} 157 */ 158 159 /** @defgroup PWR_PIN_Pull PWR Pin Pull configuration 160 * @{ 161 */ 162 #define PWR_PIN_NO_PULL (0x0U) 163 #define PWR_PIN_PULL_UP (0x1U) 164 #define PWR_PIN_PULL_DOWN (0x2U) 165 /** 166 * @} 167 */ 168 169 /** @defgroup PWR_Wakeup_Pins_Flags PWR Wakeup Pins Flags. 170 * @{ 171 */ 172 #define PWR_WAKEUP_FLAG1 PWR_WKUPSR_WKUPF1 /*!< Wakeup flag on PA0 */ 173 #define PWR_WAKEUP_FLAG2 PWR_WKUPSR_WKUPF2 /*!< Wakeup flag on PA2 */ 174 #define PWR_WAKEUP_FLAG3 PWR_WKUPSR_WKUPF3 /*!< Wakeup flag on PC13 */ 175 #define PWR_WAKEUP_FLAG4 PWR_WKUPSR_WKUPF4 /*!< Wakeup flag on PD2 */ 176 177 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPSR_WKUPF1 | PWR_WKUPSR_WKUPF2 |\ 178 PWR_WKUPSR_WKUPF3 | PWR_WKUPSR_WKUPF4) 179 /** 180 * @} 181 */ 182 183 /** @defgroup PWR_Items PWR Items 184 * @{ 185 */ 186 187 /* Use the PWR_SECCFGR bits definition offset for both Secure and Privilege because 188 it is the same offset value for the same item */ 189 #define PWR_ITEM_0 PWR_SECCFGR_SEC0 /*!< System supply configuration secure/privilege protection */ 190 #define PWR_ITEM_1 PWR_SECCFGR_SEC1 /*!< Programmable voltage detector secure/privilege protection */ 191 #define PWR_ITEM_2 PWR_SECCFGR_SEC2 /*!< VDDCORE monitor secure/privilege protection */ 192 #define PWR_ITEM_3 PWR_SECCFGR_SEC3 /*!< TCM and FLEXMEM low power control secure/privilege protection */ 193 #define PWR_ITEM_4 PWR_SECCFGR_SEC4 /*!< Voltage scaling selection secure/privilege protection */ 194 #define PWR_ITEM_5 PWR_SECCFGR_SEC5 /*!< Backup domain secure/privilege protection */ 195 #define PWR_ITEM_6 PWR_SECCFGR_SEC6 /*!< CPU power control secure/privilege protection */ 196 #define PWR_ITEM_7 PWR_SECCFGR_SEC7 /*!< Peripheral voltage monitor secure/privilege protection */ 197 #define PWR_ITEM_WKUP1 PWR_SECCFGR_WKUPSEC1 /*!< WKUP1 pin secure/privilege protection */ 198 #define PWR_ITEM_WKUP2 PWR_SECCFGR_WKUPSEC2 /*!< WKUP2 pin secure/privilege protection */ 199 #define PWR_ITEM_WKUP3 PWR_SECCFGR_WKUPSEC3 /*!< WKUP3 pin secure/privilege protection */ 200 #define PWR_ITEM_WKUP4 PWR_SECCFGR_WKUPSEC4 /*!< WKUP4 pin secure/privilege protection */ 201 202 #define PWR_ITEM_ALL (PWR_ITEM_0 | PWR_ITEM_1 | PWR_ITEM_2 | PWR_ITEM_3 | PWR_ITEM_4 | PWR_ITEM_5 | \ 203 PWR_ITEM_6 | PWR_ITEM_7 | PWR_ITEM_WKUP1 | PWR_ITEM_WKUP2 | PWR_ITEM_WKUP3 | \ 204 PWR_ITEM_WKUP4) 205 /** 206 * @} 207 */ 208 209 /** @defgroup PWR_Attributes PWR Attributes 210 * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes 211 * @{ 212 */ 213 /* Defines attribute */ 214 #define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ 215 #define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ 216 217 #define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ 218 #define PWR_NSEC_NPRIV PWR_ITEM_ATTR_NSEC_PRIV_MASK /*!< NSecure and NPrivileged attribute */ 219 #define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ 220 #define PWR_SEC_NPRIV PWR_ITEM_ATTR_SEC_PRIV_MASK /*!< Secure and NPrivileged attribute */ 221 /** 222 * @} 223 */ 224 225 /** @defgroup PWR_Flag PWR Status Flags 226 * Elements values convention: 0000 00XX XXXX XXXY YYYYb 227 * - Y YYYY : Flag position in the XXX register (5 bits) 228 * - XX XXXX XXX : Status register (9 bits) 229 * - 000000001: CR2 register 230 * - 000000010: VOSCR register 231 * - 000000100: CR3 register 232 * - 000001000: BDCR1 register 233 * - 000010000: CPUCR register 234 * - 000100000: SVMCR1 register 235 * - 001000000: SVMCR2 register 236 * - 010000000: SVMCR3 register 237 * - 100000000: WKUPSR register 238 * @{ 239 */ 240 /* CR2 */ 241 #define PWR_FLAG_PVDO (0x0028U) /*!< Programmable voltage detect output */ 242 243 /* VOSCR */ 244 #define PWR_FLAG_ACTVOSRDY (0x0051U) /*!< Voltage levels ready bit */ 245 #define PWR_FLAG_ACTVOS (0x0050U) /*!< Programmable voltage detect output */ 246 #define PWR_FLAG_VOSRDY (0x0041U) /*!< VOS Ready bit for VCORE voltage scaling output selection */ 247 248 /* CR3 */ 249 #define PWR_FLAG_VCOREH (0x0089U) /*!< VDDCORE level monitoring versus high threshold */ 250 #define PWR_FLAG_VCOREL (0x0088U) /*!< VDDCORE level monitoring versus low threshold */ 251 252 /* BDCR1 */ 253 #define PWR_FLAG_TEMPH (0x0113U) /*!< Temperature level monitoring versus high threshold */ 254 #define PWR_FLAG_TEMPL (0x0112U) /*!< Temperature level monitoring versus low threshold */ 255 #define PWR_FLAG_VBATH (0x0111U) /*!< VBAT level monitoring versus high threshold */ 256 #define PWR_FLAG_VBATL (0x0110U) /*!< VBAT level monitoring versus low threshold */ 257 258 /* CPUCR */ 259 #define PWR_FLAG_SBF (0x0209U) /*!< System Standby flag */ 260 #define PWR_FLAG_STOPF (0x0208U) /*!< System Stop flag */ 261 262 /* SVMCR1 */ 263 #define PWR_FLAG_VDDIO4RDY (0x0410U) /*!< VDDIO4 ready */ 264 265 266 /* SVMCR2 */ 267 #define PWR_FLAG_VDDIO5RDY (0x0810U) /*!< VDDIO5 ready */ 268 269 /* SVMCR3 */ 270 #define PWR_FLAG_ARDY (0x1014U) /*!< VDDA18ADC ready */ 271 #define PWR_FLAG_USB33RDY (0x1012U) /*!< VDD33USB ready */ 272 #define PWR_FLAG_VDDIO3RDY (0x1011U) /*!< VDDIO3 ready */ 273 #define PWR_FLAG_VDDIO2RDY (0x1010U) /*!< VDDIO2 ready */ 274 275 /* WKUPSR */ 276 #define PWR_FLAG_WKUPF4 (0x2004U) /*!< Wakeup event on wakeup pin 4 */ 277 #define PWR_FLAG_WKUPF3 (0x2003U) /*!< Wakeup event on wakeup pin 3 */ 278 #define PWR_FLAG_WKUPF2 (0x2002U) /*!< Wakeup event on wakeup pin 2 */ 279 #define PWR_FLAG_WKUPF1 (0x2001U) /*!< Wakeup event on wakeup pin 1 */ 280 /** 281 * @} 282 */ 283 284 /** 285 * @} 286 */ 287 /* Exported macro ------------------------------------------------------------*/ 288 /** @defgroup PWR_Exported_Macro PWR Exported Macro 289 * @{ 290 */ 291 292 /** @brief Check whether or not a specific PWR flag is set. 293 * @param __FLAG__ specifies the flag to check. 294 * This parameter can be one of the following values: 295 * @arg PWR_FLAG_PVDO: This flag is valid only if PVD 296 * is enabled by the HAL_PWR_EnablePVD()function. 297 * The PVD is stopped by STANDBY mode. 298 * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the regulator voltage 299 * scaling output selection is ready. 300 * @arg PWR_FLAG_ACTVOS: This flag indicates that the regulator voltage 301 * scaling output selection is ready. 302 * @arg PWR_FLAG_VOSRDY When an internal regulator is used, this bit indicates 303 * that all the features allowed by the selected VOS can be used. 304 * @arg PWR_FLAG_VCOREH: This flag indicates if the VDDCORE level is above 305 * the high monitoring threshold. 306 * @arg PWR_FLAG_VCOREL This flag indicates if the VDDCORE level is above 307 * the low monitoring threshold. 308 * @arg PWR_FLAG_TEMPH: This flag indicates if the temperature level is above 309 * the high monitoring threshold. 310 * @arg PWR_FLAG_TEMPL This flag indicates if the temperature level is above 311 * the low monitoring threshold. 312 * @arg PWR_FLAG_VBATH: This flag indicates if the VBAT level is above 313 * the high monitoring threshold. 314 * @arg PWR_FLAG_VBATL: This flag indicates if the VBAT level is above 315 * the low monitoring threshold. 316 * @arg PWR_FLAG_SBF: Standby mode flag. 317 * @arg PWR_FLAG_STOPF: STOP mode flag. 318 * @arg PWR_FLAG_VDDIO5RDY: This flag indicates if the VDDIO5 is ready. 319 * @arg PWR_FLAG_VDDIO4RDY: This flag indicates if the VDDIO4 is ready. 320 * @arg PWR_FLAG_VDDIO3RDY: This flag indicates if the VDDIO3 is ready. 321 * @arg PWR_FLAG_VDDIO2RDY: This flag indicates if the VDDIO2 is ready. 322 * @arg PWR_FLAG_ARDY: This flag indicates if the VDDA18ADC is ready. 323 * @arg PWR_FLAG_USB33RDY: This flag indicates if the VDD33USB is ready. 324 * @arg PWR_FLAG_WUF1: This flag indicates a wakeup event was 325 * received from WKUP1 pin. 326 * @arg PWR_FLAG_WUF2: This flag indicates a wakeup event was 327 * received from WKUP2 pin. 328 * @arg PWR_FLAG_WUF3: This flag indicates a wakeup event was 329 * received from WKUP3 pin. 330 * @arg PWR_FLAG_WUF4: This flag indicates a wakeup event was 331 * received from WKUP4 pin. 332 * @retval The (__FLAG__) state (TRUE or FALSE). 333 */ 334 #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ 335 ((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CR2 & PWR_CR2_PVDO) == PWR_CR2_PVDO) : \ 336 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->VOSCR & PWR_VOSCR_ACTVOSRDY) == PWR_VOSCR_ACTVOSRDY) : \ 337 ((__FLAG__) == PWR_FLAG_ACTVOS) ? ((PWR->VOSCR & PWR_VOSCR_ACTVOS) == PWR_VOSCR_ACTVOS) : \ 338 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->VOSCR & PWR_VOSCR_VOSRDY) == PWR_VOSCR_VOSRDY) : \ 339 ((__FLAG__) == PWR_FLAG_VCOREH) ? ((PWR->CR3 & PWR_CR3_VCOREH) == PWR_CR3_VCOREH) : \ 340 ((__FLAG__) == PWR_FLAG_VCOREL) ? ((PWR->CR3 & PWR_CR3_VCOREL) == PWR_CR3_VCOREL) : \ 341 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPH) == PWR_BDCR1_TEMPH) : \ 342 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPL) == PWR_BDCR1_TEMPL) : \ 343 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->BDCR1 & PWR_BDCR1_VBATH) == PWR_BDCR1_VBATH) : \ 344 ((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->BDCR1 & PWR_BDCR1_VBATL) == PWR_BDCR1_VBATL) : \ 345 ((__FLAG__) == PWR_FLAG_SBF) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \ 346 ((__FLAG__) == PWR_FLAG_STOPF) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \ 347 ((__FLAG__) == PWR_FLAG_VDDIO4RDY) ? ((PWR->SVMCR1 & PWR_SVMCR1_VDDIO4RDY) == PWR_SVMCR1_VDDIO4RDY) : \ 348 ((__FLAG__) == PWR_FLAG_VDDIO5RDY) ? ((PWR->SVMCR2 & PWR_SVMCR2_VDDIO5RDY) == PWR_SVMCR2_VDDIO5RDY) : \ 349 ((__FLAG__) == PWR_FLAG_ARDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_ARDY) == PWR_SVMCR3_ARDY) : \ 350 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_USB33RDY) == PWR_SVMCR3_USB33RDY) : \ 351 ((__FLAG__) == PWR_FLAG_VDDIO3RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO3RDY) == PWR_SVMCR3_VDDIO3RDY) : \ 352 ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? ((PWR->SVMCR3 & PWR_SVMCR3_VDDIO2RDY) == PWR_SVMCR3_VDDIO2RDY) : \ 353 ((__FLAG__) == PWR_FLAG_WKUPF4) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4) == PWR_WKUPSR_WKUPF4) : \ 354 ((__FLAG__) == PWR_FLAG_WKUPF3) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF3) == PWR_WKUPSR_WKUPF3) : \ 355 ((__FLAG__) == PWR_FLAG_WKUPF2) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF2) == PWR_WKUPSR_WKUPF2) : \ 356 ((__FLAG__) == PWR_FLAG_WKUPF1) ? ((PWR->WKUPSR & PWR_WKUPSR_WKUPF1) == PWR_WKUPSR_WKUPF1) : \ 357 ((PWR->WKUPSR & PWR_WKUPSR_WKUPF4) == PWR_WKUPSR_WKUPF4)) 358 359 /** @brief Clear PWR flags. 360 * @param __FLAG__: specifies the flag to clear. 361 * This parameter can be one of the following values: 362 * @arg PWR_FLAG_STOPF : Stop flag. 363 * Indicates that the device was resumed from Stop mode. 364 * @arg PWR_FLAG_SBF : Standby flag. 365 * Indicates that the device was resumed from Standby mode. 366 * @retval None. 367 */ 368 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ 369 ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \ 370 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)) : \ 371 (SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF))) 372 373 /** @brief Check PWR wake up flags are set or not. 374 * @param __FLAG__: specifies the wake up flag to check. 375 * This parameter can be one of the following values: 376 * @arg PWR_FLAG_WKUP1 : This parameter gets Wake up line 1 flag. 377 * @arg PWR_FLAG_WKUP2 : This parameter gets Wake up line 2 flag. 378 * @arg PWR_FLAG_WKUP3 : This parameter gets Wake up line 3 flag. 379 * @arg PWR_FLAG_WKUP4 : This parameter gets Wake up line 4 flag. 380 * @arg PWR_FLAG_WKUP : This parameter gets Wake up lines 1 to 4 flags. 381 * @retval The (__FLAG__) state (TRUE or FALSE). 382 */ 383 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0U : 1U) 384 385 /** @brief Clear CPU PWR wake up flags. 386 * @param __FLAG__ : Specifies the wake up flag to be cleared. 387 * This parameter can be one of the following values : 388 * @arg PWR_FLAG_WKUP1 : This parameter clears Wake up line 1 flag. 389 * @arg PWR_FLAG_WKUP2 : This parameter clears Wake up line 2 flag. 390 * @arg PWR_FLAG_WKUP3 : This parameter clears Wake up line 3 flag. 391 * @arg PWR_FLAG_WKUP4 : This parameter clears Wake up line 4 flag. 392 * @arg PWR_FLAG_WKUP : This parameter clears Wake up lines 1 to 4 flags. 393 * @retval None. 394 */ 395 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) 396 397 /** 398 * @brief Enable the PVD Extended Interrupt Line. 399 * @retval None. 400 */ 401 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD) 402 403 /** 404 * @brief Disable the PVD Extended Interrupt Line. 405 * @retval None. 406 */ 407 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR3, PWR_EXTI_LINE_PVD) 408 409 /** 410 * @brief Enable the PVD Event Line. 411 * @retval None. 412 */ 413 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD) 414 415 /** 416 * @brief Disable the PVD Event Line. 417 * @retval None. 418 */ 419 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR3, PWR_EXTI_LINE_PVD) 420 421 /** 422 * @brief Enable the PVD Extended Interrupt Rising Trigger. 423 * @retval None. 424 */ 425 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD) 426 427 /** 428 * @brief Disable the PVD Extended Interrupt Rising Trigger. 429 * @retval None. 430 */ 431 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR3, PWR_EXTI_LINE_PVD) 432 433 /** 434 * @brief Enable the PVD Extended Interrupt Falling Trigger. 435 * @retval None. 436 */ 437 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD) 438 439 /** 440 * @brief Disable the PVD Extended Interrupt Falling Trigger. 441 * @retval None. 442 */ 443 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR3, PWR_EXTI_LINE_PVD) 444 445 /** 446 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 447 * @retval None. 448 */ 449 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 450 do \ 451 { \ 452 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 453 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 454 } while(0); 455 456 /** 457 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 458 * @retval None. 459 */ 460 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 461 do \ 462 { \ 463 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 464 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 465 } while(0); 466 467 /** 468 * @brief Check whether or not the PVD EXTI interrupt Rising flag is set. 469 * @retval EXTI PVD Line Status. 470 */ 471 #define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR3 & PWR_EXTI_LINE_PVD) 472 473 /** 474 * @brief Check whether or not the PVD EXTI interrupt Falling flag is set. 475 * @retval EXTI PVD Line Status. 476 */ 477 #define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR3 & PWR_EXTI_LINE_PVD) 478 479 /** 480 * @brief Clear the PVD EXTI interrupt Rising flag. 481 * @retval None 482 */ 483 #define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR3, PWR_EXTI_LINE_PVD) 484 485 /** 486 * @brief Clear the PVD EXTI interrupt Falling flag. 487 * @retval None 488 */ 489 #define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR3, PWR_EXTI_LINE_PVD) 490 491 /** 492 * @brief Generates a Software interrupt on PVD EXTI line. 493 * @retval None. 494 */ 495 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER3, PWR_EXTI_LINE_PVD) 496 /** 497 * @} 498 */ 499 500 /* Private types -------------------------------------------------------------*/ 501 /* Private variables ---------------------------------------------------------*/ 502 /* Private constants ---------------------------------------------------------*/ 503 /** @defgroup PWR_Private_Constants PWR Private Constants 504 * @{ 505 */ 506 507 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line 508 * @{ 509 */ 510 #define PWR_EXTI_LINE_PVD EXTI_IMR3_IM66 /*!< External interrupt line 66 connected to the PVD EXTI Line */ 511 /** 512 * @} 513 */ 514 515 /** 516 * @} 517 */ 518 /* Private macros ------------------------------------------------------------*/ 519 /** @defgroup PWR_Private_Macros PWR Private Macros 520 * @{ 521 */ 522 523 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters 524 * @{ 525 */ 526 527 /* Check PVD mode parameter */ 528 #define IS_PWR_PVD_MODE(__MODE__) (((__MODE__) == PWR_PVD_MODE_IT_RISING) ||\ 529 ((__MODE__) == PWR_PVD_MODE_IT_FALLING) ||\ 530 ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 531 ((__MODE__) == PWR_PVD_MODE_EVENT_RISING) ||\ 532 ((__MODE__) == PWR_PVD_MODE_EVENT_FALLING) ||\ 533 ((__MODE__) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ 534 ((__MODE__) == PWR_PVD_MODE_NORMAL)) 535 536 /* Check Sleep mode entry parameter */ 537 #define IS_PWR_SLEEP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_SLEEPENTRY_WFI) ||\ 538 ((__ENTRY__) == PWR_SLEEPENTRY_WFE) ||\ 539 ((__ENTRY__) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) 540 541 /* Check Stop mode mode entry parameter */ 542 #define IS_PWR_STOP_ENTRY(__ENTRY__) (((__ENTRY__) == PWR_STOPENTRY_WFI) ||\ 543 ((__ENTRY__) == PWR_STOPENTRY_WFE) ||\ 544 ((__ENTRY__) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) 545 546 /* Check wake up pin parameter */ 547 #define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) ||\ 548 ((__PIN__) == PWR_WAKEUP_PIN2) ||\ 549 ((__PIN__) == PWR_WAKEUP_PIN3) ||\ 550 ((__PIN__) == PWR_WAKEUP_PIN4) ||\ 551 ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) ||\ 552 ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) ||\ 553 ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) ||\ 554 ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) ||\ 555 ((__PIN__) == PWR_WAKEUP_PIN1_LOW) ||\ 556 ((__PIN__) == PWR_WAKEUP_PIN2_LOW) ||\ 557 ((__PIN__) == PWR_WAKEUP_PIN3_LOW) ||\ 558 ((__PIN__) == PWR_WAKEUP_PIN4_LOW)) 559 560 /* Check wake up pin polarity parameter */ 561 #define IS_PWR_WAKEUP_PIN_POLARITY(__POLARITY__) (((__POLARITY__) == PWR_PIN_POLARITY_HIGH) ||\ 562 ((__POLARITY__) == PWR_PIN_POLARITY_LOW)) 563 564 /* Check wake up pin pull configuration parameter */ 565 #define IS_PWR_WAKEUP_PIN_PULL(__PULL__) (((__PULL__) == PWR_PIN_NO_PULL) ||\ 566 ((__PULL__) == PWR_PIN_PULL_UP) ||\ 567 ((__PULL__) == PWR_PIN_PULL_DOWN)) 568 569 /* Check wake up flag parameter */ 570 #define IS_PWR_WAKEUP_FLAG(__FLAG__) (((__FLAG__) == PWR_WAKEUP_FLAG1) ||\ 571 ((__FLAG__) == PWR_WAKEUP_FLAG2) ||\ 572 ((__FLAG__) == PWR_WAKEUP_FLAG3) ||\ 573 ((__FLAG__) == PWR_WAKEUP_FLAG4) ||\ 574 ((__FLAG__) == PWR_WAKEUP_FLAG_ALL)) 575 576 577 /* PWR Secure/Privilege items check macro */ 578 #define IS_PWR_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & (~PWR_ITEM_ALL)) == 0U) && ((__ITEM__) != 0U)) 579 580 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 581 /* PWR attribute check macro (Secure) */ 582 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES)& \ 583 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && \ 584 (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) 585 #else 586 /* PWR attribute check macro (NSecure) */ 587 #define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) 588 #endif /* __ARM_FEATURE_CMSE */ 589 590 /** 591 * @} 592 */ 593 594 /** 595 * @} 596 */ 597 598 /* Include PWR HAL Extended module */ 599 #include "stm32n6xx_hal_pwr_ex.h" 600 601 /* Exported functions --------------------------------------------------------*/ 602 603 /** @addtogroup PWR_Exported_Functions PWR Exported Functions 604 * @{ 605 */ 606 607 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions 608 * @{ 609 */ 610 /* Initialization and de-initialization functions *****************************/ 611 void HAL_PWR_DeInit(void); 612 void HAL_PWR_EnableBkUpAccess(void); 613 void HAL_PWR_DisableBkUpAccess(void); 614 /** 615 * @} 616 */ 617 618 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions 619 * @{ 620 */ 621 /* Peripheral Control Functions **********************************************/ 622 /* PVD configuration */ 623 void HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *pConfigPVD); 624 void HAL_PWR_EnablePVD(void); 625 void HAL_PWR_DisablePVD(void); 626 627 /* WakeUp pins configuration */ 628 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); 629 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 630 uint32_t HAL_PWR_GetWakeupFlag(uint32_t WakeUpFlag); 631 HAL_StatusTypeDef HAL_PWR_ClearWakeupFlag(uint32_t WakeUpFlag); 632 633 /* Low Power modes entry */ 634 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 635 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 636 void HAL_PWR_EnterSTANDBYMode(void); 637 638 /* Cortex System Control functions *******************************************/ 639 void HAL_PWR_EnableSleepOnExit(void); 640 void HAL_PWR_DisableSleepOnExit(void); 641 void HAL_PWR_EnableSEVOnPend(void); 642 void HAL_PWR_DisableSEVOnPend(void); 643 644 /* Interrupt handler functions ************************************************/ 645 void HAL_PWR_PVD_Rising_Callback(void); 646 void HAL_PWR_PVD_Falling_Callback(void); 647 void HAL_PWR_WAKEUP_PIN_IRQHandler(void); 648 void HAL_PWR_WKUP1_Callback(void); 649 void HAL_PWR_WKUP2_Callback(void); 650 void HAL_PWR_WKUP3_Callback(void); 651 void HAL_PWR_WKUP4_Callback(void); 652 /** 653 * @} 654 */ 655 656 /** @addtogroup PWR_Exported_Functions_Group3 657 * @{ 658 */ 659 /* Privileges and security configuration functions ****************************/ 660 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); 661 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 670 /** 671 * @} 672 */ 673 674 /** 675 * @} 676 */ 677 678 #ifdef __cplusplus 679 } 680 #endif /* __cplusplus */ 681 682 #endif /* STM32N6xx_HAL_PWR_H */ 683 684
