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Searched refs:SPI_SR_UDR_Msk (Results 1 – 25 of 260) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4387 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4388 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f101xb.h4449 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4450 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f100xb.h4854 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4855 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f102x6.h5506 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
5507 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f100xe.h5368 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
5369 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f101xg.h5454 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
5455 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f101xe.h5380 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
5381 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f102xb.h5560 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
5561 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h4755 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4756 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l010x8.h4430 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4431 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l010xb.h4478 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4479 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l011xx.h4495 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4496 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l021xx.h4632 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4633 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l031xx.h4618 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4619 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l051xx.h4727 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4728 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l010x4.h4386 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4387 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l010x6.h4438 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4439 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l081xx.h4998 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4999 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32l071xx.h4861 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4862 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f031x6.h4010 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4011 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f038xx.h3982 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
3983 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f058xx.h4482 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4483 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32f051x8.h4510 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4511 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h4826 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4827 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
Dstm32c031xx.h4989 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ macro
4990 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */

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