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Searched refs:RI_CMR5_PG_Pos (Results 1 – 16 of 16) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h6252 #define RI_CMR5_PG_Pos (0U) macro
6253 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6255 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6256 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6257 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6258 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6259 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6260 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6261 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6262 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xc.h6441 #define RI_CMR5_PG_Pos (0U) macro
6442 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6444 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6445 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6446 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6447 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6448 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6449 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6450 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6451 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xca.h6505 #define RI_CMR5_PG_Pos (0U) macro
6506 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6508 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6509 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6510 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6511 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6512 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6513 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6514 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6515 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xdx.h6570 #define RI_CMR5_PG_Pos (0U) macro
6571 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6573 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6574 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6575 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6576 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6577 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6578 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6579 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6580 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xe.h6570 #define RI_CMR5_PG_Pos (0U) macro
6571 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6573 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6574 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6575 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6576 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6577 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6578 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6579 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6580 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xc.h6570 #define RI_CMR5_PG_Pos (0U) macro
6571 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6573 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6574 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6575 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6576 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6577 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6578 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6579 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6580 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xca.h6655 #define RI_CMR5_PG_Pos (0U) macro
6656 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6658 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6659 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6660 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6661 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6662 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6663 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6664 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6665 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xdx.h6720 #define RI_CMR5_PG_Pos (0U) macro
6721 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6723 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6724 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6725 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6726 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6727 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6728 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6729 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6730 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xe.h6720 #define RI_CMR5_PG_Pos (0U) macro
6721 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6723 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6724 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6725 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6726 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6727 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6728 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6729 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6730 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xc.h6709 #define RI_CMR5_PG_Pos (0U) macro
6710 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6712 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6713 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6714 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6715 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6716 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6717 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6718 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6719 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xca.h6794 #define RI_CMR5_PG_Pos (0U) macro
6795 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6797 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6798 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6799 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6800 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6801 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6802 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6803 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6804 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xdx.h6859 #define RI_CMR5_PG_Pos (0U) macro
6860 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6862 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6863 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6864 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6865 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6866 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6867 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6868 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6869 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xe.h6859 #define RI_CMR5_PG_Pos (0U) macro
6860 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
6862 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
6863 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
6864 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
6865 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
6866 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
6867 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
6868 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
6869 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l151xd.h7205 #define RI_CMR5_PG_Pos (0U) macro
7206 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
7208 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
7209 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
7210 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
7211 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
7212 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
7213 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
7214 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
7215 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l152xd.h7355 #define RI_CMR5_PG_Pos (0U) macro
7356 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
7358 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
7359 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
7360 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
7361 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
7362 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
7363 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
7364 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
7365 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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Dstm32l162xd.h7494 #define RI_CMR5_PG_Pos (0U) macro
7495 #define RI_CMR5_PG_Msk (0xFFFFUL << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
7497 #define RI_CMR5_PG_0 (0x0001UL << RI_CMR5_PG_Pos) /*!< 0x00000001 */
7498 #define RI_CMR5_PG_1 (0x0002UL << RI_CMR5_PG_Pos) /*!< 0x00000002 */
7499 #define RI_CMR5_PG_2 (0x0004UL << RI_CMR5_PG_Pos) /*!< 0x00000004 */
7500 #define RI_CMR5_PG_3 (0x0008UL << RI_CMR5_PG_Pos) /*!< 0x00000008 */
7501 #define RI_CMR5_PG_4 (0x0010UL << RI_CMR5_PG_Pos) /*!< 0x00000010 */
7502 #define RI_CMR5_PG_5 (0x0020UL << RI_CMR5_PG_Pos) /*!< 0x00000020 */
7503 #define RI_CMR5_PG_6 (0x0040UL << RI_CMR5_PG_Pos) /*!< 0x00000040 */
7504 #define RI_CMR5_PG_7 (0x0080UL << RI_CMR5_PG_Pos) /*!< 0x00000080 */
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