Searched refs:RI_CICR5_PG_Pos (Results 1 – 16 of 16) sorted by relevance
6273 #define RI_CICR5_PG_Pos (0U) macro6274 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6276 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6277 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6278 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6279 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6280 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6281 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6282 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6283 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6462 #define RI_CICR5_PG_Pos (0U) macro6463 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6465 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6466 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6467 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6468 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6469 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6470 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6471 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6472 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6526 #define RI_CICR5_PG_Pos (0U) macro6527 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6529 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6530 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6531 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6532 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6533 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6534 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6535 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6536 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6591 #define RI_CICR5_PG_Pos (0U) macro6592 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6594 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6595 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6596 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6597 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6598 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6599 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6600 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6601 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6676 #define RI_CICR5_PG_Pos (0U) macro6677 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6679 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6680 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6681 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6682 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6683 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6684 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6685 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6686 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6741 #define RI_CICR5_PG_Pos (0U) macro6742 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6744 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6745 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6746 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6747 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6748 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6749 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6750 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6751 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6730 #define RI_CICR5_PG_Pos (0U) macro6731 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6733 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6734 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6735 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6736 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6737 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6738 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6739 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6740 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6815 #define RI_CICR5_PG_Pos (0U) macro6816 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6818 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6819 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6820 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6821 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6822 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6823 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6824 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6825 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
6880 #define RI_CICR5_PG_Pos (0U) macro6881 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */6883 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */6884 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */6885 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */6886 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */6887 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */6888 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */6889 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */6890 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
7226 #define RI_CICR5_PG_Pos (0U) macro7227 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */7229 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */7230 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */7231 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */7232 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */7233 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */7234 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */7235 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */7236 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
7376 #define RI_CICR5_PG_Pos (0U) macro7377 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */7379 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */7380 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */7381 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */7382 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */7383 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */7384 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */7385 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */7386 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
7515 #define RI_CICR5_PG_Pos (0U) macro7516 #define RI_CICR5_PG_Msk (0xFFFFUL << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */7518 #define RI_CICR5_PG_0 (0x0001UL << RI_CICR5_PG_Pos) /*!< 0x00000001 */7519 #define RI_CICR5_PG_1 (0x0002UL << RI_CICR5_PG_Pos) /*!< 0x00000002 */7520 #define RI_CICR5_PG_2 (0x0004UL << RI_CICR5_PG_Pos) /*!< 0x00000004 */7521 #define RI_CICR5_PG_3 (0x0008UL << RI_CICR5_PG_Pos) /*!< 0x00000008 */7522 #define RI_CICR5_PG_4 (0x0010UL << RI_CICR5_PG_Pos) /*!< 0x00000010 */7523 #define RI_CICR5_PG_5 (0x0020UL << RI_CICR5_PG_Pos) /*!< 0x00000020 */7524 #define RI_CICR5_PG_6 (0x0040UL << RI_CICR5_PG_Pos) /*!< 0x00000040 */7525 #define RI_CICR5_PG_7 (0x0080UL << RI_CICR5_PG_Pos) /*!< 0x00000080 */[all …]
