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Searched refs:RI_CICR4_PF_Pos (Results 1 – 16 of 16) sorted by relevance

/hal_stm32-latest/stm32cube/stm32l1xx/soc/
Dstm32l100xc.h6210 #define RI_CICR4_PF_Pos (0U) macro
6211 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6213 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6214 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6215 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6216 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6217 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6218 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6219 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6220 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xc.h6399 #define RI_CICR4_PF_Pos (0U) macro
6400 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6402 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6403 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6404 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6405 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6406 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6407 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6408 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6409 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xca.h6463 #define RI_CICR4_PF_Pos (0U) macro
6464 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6466 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6467 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6468 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6469 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6470 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6471 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6472 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6473 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xdx.h6528 #define RI_CICR4_PF_Pos (0U) macro
6529 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6531 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6532 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6533 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6534 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6535 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6536 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6537 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6538 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xe.h6528 #define RI_CICR4_PF_Pos (0U) macro
6529 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6531 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6532 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6533 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6534 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6535 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6536 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6537 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6538 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xc.h6528 #define RI_CICR4_PF_Pos (0U) macro
6529 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6531 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6532 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6533 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6534 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6535 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6536 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6537 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6538 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xca.h6613 #define RI_CICR4_PF_Pos (0U) macro
6614 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6616 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6617 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6618 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6619 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6620 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6621 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6622 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6623 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xdx.h6678 #define RI_CICR4_PF_Pos (0U) macro
6679 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6681 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6682 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6683 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6684 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6685 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6686 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6687 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6688 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xe.h6678 #define RI_CICR4_PF_Pos (0U) macro
6679 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6681 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6682 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6683 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6684 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6685 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6686 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6687 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6688 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xc.h6667 #define RI_CICR4_PF_Pos (0U) macro
6668 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6670 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6671 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6672 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6673 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6674 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6675 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6676 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6677 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xca.h6752 #define RI_CICR4_PF_Pos (0U) macro
6753 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6755 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6756 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6757 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6758 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6759 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6760 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6761 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6762 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xdx.h6817 #define RI_CICR4_PF_Pos (0U) macro
6818 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6820 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6821 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6822 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6823 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6824 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6825 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6826 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6827 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xe.h6817 #define RI_CICR4_PF_Pos (0U) macro
6818 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
6820 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
6821 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
6822 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
6823 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
6824 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
6825 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
6826 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
6827 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l151xd.h7163 #define RI_CICR4_PF_Pos (0U) macro
7164 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7166 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7167 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7168 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7169 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7170 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7171 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7172 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7173 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l152xd.h7313 #define RI_CICR4_PF_Pos (0U) macro
7314 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7316 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7317 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7318 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7319 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7320 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7321 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7322 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7323 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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Dstm32l162xd.h7452 #define RI_CICR4_PF_Pos (0U) macro
7453 #define RI_CICR4_PF_Msk (0xFFFFUL << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
7455 #define RI_CICR4_PF_0 (0x0001UL << RI_CICR4_PF_Pos) /*!< 0x00000001 */
7456 #define RI_CICR4_PF_1 (0x0002UL << RI_CICR4_PF_Pos) /*!< 0x00000002 */
7457 #define RI_CICR4_PF_2 (0x0004UL << RI_CICR4_PF_Pos) /*!< 0x00000004 */
7458 #define RI_CICR4_PF_3 (0x0008UL << RI_CICR4_PF_Pos) /*!< 0x00000008 */
7459 #define RI_CICR4_PF_4 (0x0010UL << RI_CICR4_PF_Pos) /*!< 0x00000010 */
7460 #define RI_CICR4_PF_5 (0x0020UL << RI_CICR4_PF_Pos) /*!< 0x00000020 */
7461 #define RI_CICR4_PF_6 (0x0040UL << RI_CICR4_PF_Pos) /*!< 0x00000040 */
7462 #define RI_CICR4_PF_7 (0x0080UL << RI_CICR4_PF_Pos) /*!< 0x00000080 */
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