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Searched refs:RCC_PLL3CFGR_PLL3RGE_Pos (Results 1 – 20 of 20) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h5235 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos); in LL_RCC_PLL3_SetVCOInputRange()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c1350 …nit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c2563 …nit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h12702 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
12703 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
12705 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
12706 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32h562xx.h13382 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
13383 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
13385 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
13386 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32h533xx.h13221 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
13222 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
13224 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
13225 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32h573xx.h15985 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
15986 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
15988 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
15989 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32h563xx.h15466 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
15467 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
15469 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
15470 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14547 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
14548 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
14550 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
14551 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u535xx.h14034 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
14035 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
14037 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
14038 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u575xx.h15442 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
15443 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
15445 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
15446 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u585xx.h16004 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
16005 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
16007 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
16008 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u595xx.h16470 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
16471 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
16473 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
16474 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5a5xx.h17032 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
17033 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
17035 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
17036 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5f7xx.h18003 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
18004 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
18006 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
18007 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u599xx.h20196 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
20197 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
20199 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
20200 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5g7xx.h18565 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
18566 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
18568 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
18569 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5f9xx.h21132 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
21133 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
21135 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
21136 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5a9xx.h20758 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
20759 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
20761 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
20762 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…
Dstm32u5g9xx.h21694 #define RCC_PLL3CFGR_PLL3RGE_Pos (2U) macro
21695 #define RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x0000000C…
21697 #define RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000004…
21698 #define RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) /*!< 0x00000008…