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Searched refs:RCC_PLL3CFGR_PLL3REN (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h5127 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); in LL_RCC_PLL3R_Enable()
5139 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); in LL_RCC_PLL3R_Disable()
5169 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == RCC_PLL3CFGR_PLL3REN) ? 1UL : 0UL); in LL_RCC_PLL3R_IsEnabled()
Dstm32h5xx_hal_rcc_ex.h566 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h5072 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); in LL_RCC_PLL3_EnableDomain_HSPI_LTDC()
5084 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); in LL_RCC_PLL3_DisableDomain_HSPI_LTDC()
5094 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL); in LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC()
Dstm32u5xx_hal_rcc_ex.h543 #define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c3311 …CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_… in HAL_RCCEx_DisablePLL3()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c5522 …CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_… in HAL_RCCEx_DisablePLL3()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h12730 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk macro
Dstm32h562xx.h13410 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk macro
Dstm32h533xx.h13249 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk macro
Dstm32h573xx.h16013 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk macro
Dstm32h563xx.h15494 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14570 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u535xx.h14057 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u575xx.h15465 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u585xx.h16027 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u595xx.h16493 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5a5xx.h17055 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5f7xx.h18026 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u599xx.h20219 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5g7xx.h18588 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5f9xx.h21155 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5a9xx.h20781 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro
Dstm32u5g9xx.h21717 #define RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk /*!< PLL3 DIVR … macro