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Searched refs:RCC_PLL3CFGR_PLL3QEN (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h5105 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); in LL_RCC_PLL3Q_Enable()
5117 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); in LL_RCC_PLL3Q_Disable()
5159 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == RCC_PLL3CFGR_PLL3QEN) ? 1UL : 0UL); in LL_RCC_PLL3Q_IsEnabled()
Dstm32h5xx_hal_rcc_ex.h565 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h5038 SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); in LL_RCC_PLL3_EnableDomain_48M()
5050 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); in LL_RCC_PLL3_DisableDomain_48M()
5060 return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL); in LL_RCC_PLL3_IsEnabledDomain_48M()
Dstm32u5xx_hal_rcc_ex.h542 #define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c3311 …CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_… in HAL_RCCEx_DisablePLL3()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c5522 …CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_… in HAL_RCCEx_DisablePLL3()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h12727 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk macro
Dstm32h562xx.h13407 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk macro
Dstm32h533xx.h13246 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk macro
Dstm32h573xx.h16010 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk macro
Dstm32h563xx.h15491 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14567 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u535xx.h14054 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u575xx.h15462 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u585xx.h16024 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u595xx.h16490 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5a5xx.h17052 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5f7xx.h18023 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u599xx.h20216 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5g7xx.h18585 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5f9xx.h21152 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5a9xx.h20778 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro
Dstm32u5g9xx.h21714 #define RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk /*!< PLL3 DIVQ … macro