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Searched refs:RCC_PLL2CFGR_PLL2RGE_Pos (Results 1 – 21 of 21) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4884 MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos); in LL_RCC_PLL2_SetVCOInputRange()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c1339 …nit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8526 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
8527 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
8529 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
8530 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32h523xx.h12666 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
12667 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
12669 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
12670 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32h562xx.h13346 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
13347 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
13349 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
13350 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32h533xx.h13185 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
13186 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
13188 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
13189 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32h573xx.h15949 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
15950 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
15952 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
15953 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32h563xx.h15430 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
15431 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
15433 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
15434 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c2551 …nit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14516 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
14517 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
14519 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
14520 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u535xx.h14003 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
14004 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
14006 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
14007 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u575xx.h15411 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
15412 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
15414 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
15415 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u585xx.h15973 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
15974 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
15976 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
15977 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u595xx.h16439 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
16440 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
16442 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
16443 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5a5xx.h17001 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
17002 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
17004 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
17005 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5f7xx.h17972 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
17973 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
17975 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
17976 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u599xx.h20165 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
20166 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
20168 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
20169 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5g7xx.h18534 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
18535 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
18537 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
18538 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5f9xx.h21101 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
21102 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
21104 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
21105 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5a9xx.h20727 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
20728 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
20730 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
20731 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…
Dstm32u5g9xx.h21663 #define RCC_PLL2CFGR_PLL2RGE_Pos (2U) macro
21664 #define RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x0000000C…
21666 #define RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000004…
21667 #define RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) /*!< 0x00000008…