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Searched refs:RCC_PLL2CFGR_PLL2REN (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h4776 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2R_Enable()
4788 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2R_Disable()
4818 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == RCC_PLL2CFGR_PLL2REN) ? 1UL : 0UL); in LL_RCC_PLL2R_IsEnabled()
Dstm32h5xx_hal_rcc_ex.h555 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h4648 SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2_EnableDomain_ADC()
4660 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); in LL_RCC_PLL2_DisableDomain_ADC()
4670 return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL); in LL_RCC_PLL2_IsEnabledDomain_ADC()
Dstm32u5xx_hal_rcc_ex.h533 #define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c3197 …CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_… in HAL_RCCEx_DisablePLL2()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c5397 …CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_… in HAL_RCCEx_DisablePLL2()
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8554 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
Dstm32h523xx.h12694 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
Dstm32h562xx.h13374 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
Dstm32h533xx.h13213 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
Dstm32h573xx.h15977 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
Dstm32h563xx.h15458 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14539 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u535xx.h14026 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u575xx.h15434 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u585xx.h15996 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u595xx.h16462 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5a5xx.h17024 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5f7xx.h17995 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u599xx.h20188 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5g7xx.h18557 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5f9xx.h21124 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5a9xx.h20750 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro
Dstm32u5g9xx.h21686 #define RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk /*!< PLL2 DIVR … macro