Searched refs:RCC_ICSCR2_MSITRIM0_Pos (Results 1 – 15 of 15) sorted by relevance
2352 …MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - … in LL_RCC_MSI_SetCalibTrimming()2368 … (RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); in LL_RCC_MSI_GetCalibTrimming()
1133 RCC_ICSCR2_MSITRIM0_Pos));\
1904 RCC_ICSCR2_MSITRIM0_Pos); in HAL_RCC_GetOscConfig()
14330 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro14331 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…14333 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…14334 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…14335 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…14336 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…14337 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
13817 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro13818 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…13820 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…13821 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…13822 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…13823 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…13824 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
15225 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro15226 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…15228 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…15229 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…15230 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…15231 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…15232 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
15787 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro15788 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…15790 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…15791 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…15792 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…15793 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…15794 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
16253 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro16254 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…16256 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…16257 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…16258 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…16259 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…16260 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
16815 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro16816 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…16818 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…16819 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…16820 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…16821 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…16822 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
17779 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro17780 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…17782 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…17783 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…17784 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…17785 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…17786 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
19972 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro19973 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…19975 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…19976 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…19977 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…19978 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…19979 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
18341 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro18342 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…18344 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…18345 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…18346 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…18347 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…18348 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
20908 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro20909 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…20911 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…20912 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…20913 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…20914 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…20915 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
20534 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro20535 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…20537 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…20538 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…20539 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…20540 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…20541 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
21470 #define RCC_ICSCR2_MSITRIM0_Pos (15U) macro21471 #define RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x000F8000…21473 #define RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00002000…21474 #define RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00004000…21475 #define RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00008000…21476 #define RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x0000C000…21477 #define RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) /*!< 0x00010000…
