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Searched refs:RCC_ICSCR1_MSICAL2_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14255 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
14256 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
14258 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
14259 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
14260 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
14261 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
14262 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u535xx.h13742 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
13743 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
13745 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
13746 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
13747 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
13748 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
13749 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u575xx.h15150 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
15151 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
15153 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
15154 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
15155 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
15156 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
15157 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u585xx.h15712 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
15713 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
15715 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
15716 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
15717 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
15718 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
15719 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u595xx.h16178 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
16179 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
16181 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
16182 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
16183 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
16184 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
16185 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5a5xx.h16740 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
16741 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
16743 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
16744 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
16745 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
16746 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
16747 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5f7xx.h17704 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
17705 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
17707 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
17708 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
17709 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
17710 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
17711 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u599xx.h19897 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
19898 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
19900 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
19901 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
19902 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
19903 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
19904 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5g7xx.h18266 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
18267 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
18269 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
18270 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
18271 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
18272 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
18273 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5f9xx.h20833 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
20834 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
20836 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
20837 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
20838 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
20839 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
20840 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5a9xx.h20459 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
20460 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
20462 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
20463 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
20464 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
20465 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
20466 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…
Dstm32u5g9xx.h21395 #define RCC_ICSCR1_MSICAL2_Pos (5U) macro
21396 #define RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000003E0…
21398 #define RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000020…
21399 #define RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000040…
21400 #define RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000080…
21401 #define RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x000000C0…
21402 #define RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) /*!< 0x00000100…