| /hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/ |
| D | stm32l1xx_hal_rcc.c | 760 (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) in HAL_RCC_OscConfig()
1103 plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; in HAL_RCC_GetSysClockFreq()
1258 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); in HAL_RCC_GetOscConfig()
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| /hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/ |
| D | stm32l0xx_hal_rcc.c | 821 (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) in HAL_RCC_OscConfig()
1241 plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; in HAL_RCC_GetSysClockFreq()
1409 RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); in HAL_RCC_GetOscConfig()
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| D | stm32l0xx_hal_rcc_ex.c | 471 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in HAL_RCCEx_GetPeriphCLKFreq()
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| /hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/ |
| D | stm32l1xx_ll_rcc.h | 1219 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDi… in LL_RCC_PLL_ConfigDomain_SYS()
1276 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); in LL_RCC_PLL_GetDivider()
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| D | stm32l1xx_hal_rcc.h | 1575 …MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__…
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| /hal_stm32-latest/stm32cube/stm32l0xx/soc/ |
| D | system_stm32l0xx.c | 228 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
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| D | stm32l041xx.h | 3478 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l010x8.h | 3181 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l010xb.h | 3189 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l011xx.h | 3278 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l021xx.h | 3406 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l031xx.h | 3350 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l051xx.h | 3422 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l010x4.h | 3169 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l010x6.h | 3182 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l081xx.h | 3602 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l071xx.h | 3474 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l052xx.h | 3720 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l062xx.h | 3848 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l053xx.h | 3864 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| /hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/ |
| D | stm32l0xx_ll_rcc.h | 1834 …MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDi… in LL_RCC_PLL_ConfigDomain_SYS()
1891 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); in LL_RCC_PLL_GetDivider()
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| D | stm32l0xx_hal_rcc.h | 1378 …MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__…
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| /hal_stm32-latest/stm32cube/stm32l1xx/soc/ |
| D | system_stm32l1xx.c | 231 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
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| D | stm32l152xb.h | 4016 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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| D | stm32l152xba.h | 4015 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bit… macro
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