1 /**
2 ******************************************************************************
3 * @file system_stm32l0xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l0xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 *
22 ******************************************************************************
23 * @attention
24 *
25 * Copyright (c) 2016 STMicroelectronics.
26 * All rights reserved.
27 *
28 * This software is licensed under terms that can be found in the LICENSE file
29 * in the root directory of this software component.
30 * If no LICENSE file comes with this software, it is provided AS-IS.
31 *
32 ******************************************************************************
33 */
34
35 /** @addtogroup CMSIS
36 * @{
37 */
38
39 /** @addtogroup stm32l0xx_system
40 * @{
41 */
42
43 /** @addtogroup STM32L0xx_System_Private_Includes
44 * @{
45 */
46
47 #include "stm32l0xx.h"
48
49 #if !defined (HSE_VALUE)
50 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
51 #endif /* HSE_VALUE */
52
53 #if !defined (MSI_VALUE)
54 #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
55 #endif /* MSI_VALUE */
56
57 #if !defined (HSI_VALUE)
58 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
59 #endif /* HSI_VALUE */
60
61
62 /**
63 * @}
64 */
65
66 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
67 * @{
68 */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup STM32L0xx_System_Private_Defines
75 * @{
76 */
77 /************************* Miscellaneous Configuration ************************/
78
79 /* Note: Following vector table addresses must be defined in line with linker
80 configuration. */
81 /*!< Uncomment the following line if you need to relocate the vector table
82 anywhere in Flash or Sram, else the vector table is kept at the automatic
83 remap of boot address selected */
84 /* #define USER_VECT_TAB_ADDRESS */
85
86 #if defined(USER_VECT_TAB_ADDRESS)
87 /*!< Uncomment the following line if you need to relocate your vector Table
88 in Sram else user remap will be done in Flash. */
89 /* #define VECT_TAB_SRAM */
90 #if defined(VECT_TAB_SRAM)
91 #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
92 This value must be a multiple of 0x200. */
93 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
94 This value must be a multiple of 0x200. */
95 #else
96 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
97 This value must be a multiple of 0x200. */
98 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
99 This value must be a multiple of 0x200. */
100 #endif /* VECT_TAB_SRAM */
101 #endif /* USER_VECT_TAB_ADDRESS */
102
103 /******************************************************************************/
104 /**
105 * @}
106 */
107
108 /** @addtogroup STM32L0xx_System_Private_Macros
109 * @{
110 */
111
112 /**
113 * @}
114 */
115
116 /** @addtogroup STM32L0xx_System_Private_Variables
117 * @{
118 */
119 /* This variable is updated in three ways:
120 1) by calling CMSIS function SystemCoreClockUpdate()
121 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
122 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
123 Note: If you use this function to configure the system clock; then there
124 is no need to call the 2 first functions listed above, since SystemCoreClock
125 variable is updated automatically.
126 */
127 uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
128 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
129 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
130 const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
131
132 /**
133 * @}
134 */
135
136 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
137 * @{
138 */
139
140 /**
141 * @}
142 */
143
144 /** @addtogroup STM32L0xx_System_Private_Functions
145 * @{
146 */
147
148 /**
149 * @brief Setup the microcontroller system.
150 * @param None
151 * @retval None
152 */
SystemInit(void)153 void SystemInit (void)
154 {
155 /* Configure the Vector Table location add offset address ------------------*/
156 #if defined (USER_VECT_TAB_ADDRESS)
157 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
158 #endif /* USER_VECT_TAB_ADDRESS */
159 }
160
161 /**
162 * @brief Update SystemCoreClock variable according to Clock Register Values.
163 * The SystemCoreClock variable contains the core clock (HCLK), it can
164 * be used by the user application to setup the SysTick timer or configure
165 * other parameters.
166 *
167 * @note Each time the core clock (HCLK) changes, this function must be called
168 * to update SystemCoreClock variable value. Otherwise, any configuration
169 * based on this variable will be incorrect.
170 *
171 * @note - The system frequency computed by this function is not the real
172 * frequency in the chip. It is calculated based on the predefined
173 * constant and the selected clock source:
174 *
175 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
176 * value as defined by the MSI range.
177 *
178 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
179 *
180 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
181 *
182 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
183 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
184 *
185 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
186 * 16 MHz) but the real value may vary depending on the variations
187 * in voltage and temperature.
188 *
189 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
190 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
191 * frequency of the crystal used. Otherwise, this function may
192 * have wrong result.
193 *
194 * - The result of this function could be not correct when using fractional
195 * value for HSE crystal.
196 * @param None
197 * @retval None
198 */
SystemCoreClockUpdate(void)199 void SystemCoreClockUpdate (void)
200 {
201 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
202
203 /* Get SYSCLK source -------------------------------------------------------*/
204 tmp = RCC->CFGR & RCC_CFGR_SWS;
205
206 switch (tmp)
207 {
208 case 0x00U: /* MSI used as system clock */
209 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
210 SystemCoreClock = (32768U * (1U << (msirange + 1U)));
211 break;
212 case 0x04U: /* HSI used as system clock */
213 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
214 {
215 SystemCoreClock = HSI_VALUE / 4U;
216 }
217 else
218 {
219 SystemCoreClock = HSI_VALUE;
220 }
221 break;
222 case 0x08U: /* HSE used as system clock */
223 SystemCoreClock = HSE_VALUE;
224 break;
225 default: /* PLL used as system clock */
226 /* Get PLL clock source and multiplication factor ----------------------*/
227 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
228 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
229 pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
230 plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
231
232 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
233
234 if (pllsource == 0x00U)
235 {
236 /* HSI oscillator clock selected as PLL clock entry */
237 if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
238 {
239 SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
240 }
241 else
242 {
243 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
244 }
245 }
246 else
247 {
248 /* HSE selected as PLL clock entry */
249 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
250 }
251 break;
252 }
253 /* Compute HCLK clock frequency --------------------------------------------*/
254 /* Get HCLK prescaler */
255 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
256 /* HCLK clock frequency */
257 SystemCoreClock >>= tmp;
258 }
259
260
261
262 /**
263 * @}
264 */
265
266 /**
267 * @}
268 */
269
270 /**
271 * @}
272 */
273
274
