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Searched refs:RCC_CFGR_ADCPRE_DIV8 (Results 1 – 20 of 20) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_ll_rcc.h321 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
Dstm32f1xx_hal_rcc_ex.h352 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_rcc.h466 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided …
Dstm32f3xx_hal_rcc_ex.h1675 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h890 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f101xb.h905 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f100xb.h965 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f102x6.h930 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f100xe.h1234 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f101xg.h1259 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f101xe.h1234 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f102xb.h943 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f103x6.h1005 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f103xb.h1020 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f103xe.h1389 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f103xg.h1408 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f105xc.h1392 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
Dstm32f107xc.h1472 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided b… macro
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f378xx.h7594 #define RCC_CFGR_ADCPRE_DIV8 (0x0000C000U) /*!< ADC CLK divided… macro
Dstm32f373xc.h7676 #define RCC_CFGR_ADCPRE_DIV8 (0x0000C000U) /*!< ADC CLK divided… macro