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Searched refs:RCC_CFGR2_AHB1DIS (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_bus.h378 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_EnableBusClock()
379 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_EnableBusClock()
489 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); in LL_AHB1_GRP1_DisableBusClock()
Dstm32u5xx_hal_rcc.h1288 #define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS);
1304 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
1305 tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc.h2000 SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
2002 … tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \
2049 #define __HAL_RCC_AHB1_CLK_ENABLE() CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS)
2755 #define __HAL_RCC_AHB1_IS_CLK_DISABLED() (READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS) != 0U)
Dstm32h5xx_ll_bus.h71 #define LL_AHB_BRANCH_CLK_AHB1 RCC_CFGR2_AHB1DIS
Dstm32h5xx_ll_rcc.h300 #define LL_RCC_AHB1_PERIPH_DIS RCC_CFGR2_AHB1DIS /*!< Clock Branch…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8470 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32h523xx.h12607 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32h562xx.h13287 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32h533xx.h13126 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32h573xx.h15890 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32h563xx.h15371 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14441 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u535xx.h13928 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u575xx.h15336 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u585xx.h15898 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u595xx.h16364 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5a5xx.h16926 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5f7xx.h17897 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u599xx.h20090 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5g7xx.h18459 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5f9xx.h21026 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5a9xx.h20652 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro
Dstm32u5g9xx.h21588 #define RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk /*!< AHB1 clock… macro