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Searched refs:RCC_CFGR1_SW_Pos (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h5937 #define RCC_CFGR1_SW_Pos (0U) macro
5938 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
5940 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
5941 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32wba52xx.h9711 #define RCC_CFGR1_SW_Pos (0U) macro
9712 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
9714 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
9715 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32wba54xx.h9983 #define RCC_CFGR1_SW_Pos (0U) macro
9984 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
9986 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
9987 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32wba5mxx.h10001 #define RCC_CFGR1_SW_Pos (0U) macro
10002 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
10004 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
10005 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32wba55xx.h10001 #define RCC_CFGR1_SW_Pos (0U) macro
10002 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
10004 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
10005 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8366 #define RCC_CFGR1_SW_Pos (0U) macro
8367 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
8369 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
8370 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32h523xx.h12503 #define RCC_CFGR1_SW_Pos (0U) macro
12504 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
12506 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
12507 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32h562xx.h13183 #define RCC_CFGR1_SW_Pos (0U) macro
13184 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
13186 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
13187 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32h533xx.h13022 #define RCC_CFGR1_SW_Pos (0U) macro
13023 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
13025 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
13026 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32h573xx.h15786 #define RCC_CFGR1_SW_Pos (0U) macro
15787 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
15789 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
15790 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32h563xx.h15267 #define RCC_CFGR1_SW_Pos (0U) macro
15268 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
15270 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
15271 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14384 #define RCC_CFGR1_SW_Pos (0U) macro
14385 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
14387 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
14388 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u535xx.h13871 #define RCC_CFGR1_SW_Pos (0U) macro
13872 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
13874 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
13875 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u575xx.h15279 #define RCC_CFGR1_SW_Pos (0U) macro
15280 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
15282 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
15283 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u585xx.h15841 #define RCC_CFGR1_SW_Pos (0U) macro
15842 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
15844 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
15845 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u595xx.h16307 #define RCC_CFGR1_SW_Pos (0U) macro
16308 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
16310 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
16311 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5a5xx.h16869 #define RCC_CFGR1_SW_Pos (0U) macro
16870 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
16872 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
16873 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5f7xx.h17833 #define RCC_CFGR1_SW_Pos (0U) macro
17834 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
17836 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
17837 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u599xx.h20026 #define RCC_CFGR1_SW_Pos (0U) macro
20027 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
20029 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
20030 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5g7xx.h18395 #define RCC_CFGR1_SW_Pos (0U) macro
18396 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
18398 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
18399 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5f9xx.h20962 #define RCC_CFGR1_SW_Pos (0U) macro
20963 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
20965 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
20966 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5a9xx.h20588 #define RCC_CFGR1_SW_Pos (0U) macro
20589 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
20591 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
20592 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…
Dstm32u5g9xx.h21524 #define RCC_CFGR1_SW_Pos (0U) macro
21525 #define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003…
21527 #define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001…
21528 #define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002…