Searched refs:RCC_CCIPR_TIM1SEL (Results 1 – 17 of 17) sorted by relevance
105 #if defined(RCC_CCIPR_TIM1SEL)232 #if defined(RCC_CCIPR_TIM1SEL)465 #if defined(RCC_CCIPR_TIM1SEL)470 #define RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL /*!< PLL "Q" clock selected as Timer …946 #if defined(RCC_CCIPR_TIM1SEL)954 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))961 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))1536 #if defined(RCC_CCIPR_TIM1SEL)
450 #if defined(RCC_CCIPR_TIM1SEL)454 #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*…455 #define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*…615 #if defined(RCC_CCIPR_TIM1SEL)619 #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */1981 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)2227 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)
98 #if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL)101 #elif defined(RCC_CCIPR_TIM1SEL)131 #if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)680 #if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL)1302 #if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL)
350 #if defined(RCC_CCIPR_TIM1SEL) in HAL_RCCEx_PeriphCLKConfig()490 #if defined(RCC_CCIPR_TIM1SEL) in HAL_RCCEx_GetPeriphCLKConfig()546 #if defined(RCC_CCIPR_TIM1SEL) in HAL_RCCEx_GetPeriphCLKConfig()1065 #if defined(RCC_CCIPR_TIM1SEL) in HAL_RCCEx_GetPeriphCLKFreq()1068 srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL); in HAL_RCCEx_GetPeriphCLKFreq()
330 #define RCC_TIM1CLKSOURCE_PLLQ RCC_CCIPR_TIM1SEL793 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1CLKSource__))800 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))808 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM15CLKSource__))
486 #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PC…487 #define LL_RCC_TIM1_CLKSOURCE_PLLQ (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PL…594 #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */
4722 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
4976 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
5094 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
5348 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
5482 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
5736 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
7137 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
6883 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
5616 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
6490 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
6223 #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk macro
