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Searched refs:RCC_CCIPR2_SAI1SEL_Pos (Results 1 – 25 of 25) sorted by relevance

/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba54xx.h10618 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
10619 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0…
10621 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020…
10622 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040…
10623 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080…
Dstm32wba5mxx.h10636 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
10637 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0…
10639 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020…
10640 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040…
10641 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080…
Dstm32wba55xx.h10636 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
10637 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0…
10639 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020…
10640 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040…
10641 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h12278 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
12279 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
12281 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
12282 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
12283 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l562xx.h13008 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
13009 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13011 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13012 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13013 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l4r5xx.h12972 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
12973 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
12975 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
12976 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
12977 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4r7xx.h13471 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
13472 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13474 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13475 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13476 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4s5xx.h13319 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
13320 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13322 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13323 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13324 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4s7xx.h13818 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
13819 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13821 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13822 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13823 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4p5xx.h13789 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
13790 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13792 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13793 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13794 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4q5xx.h14300 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
14301 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
14303 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
14304 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
14305 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4r9xx.h16599 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
16600 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
16602 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
16603 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
16604 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
Dstm32l4s9xx.h16946 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
16947 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
16949 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
16950 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
16951 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h15692 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
15693 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
15695 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
15696 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
15697 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u535xx.h15143 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
15144 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
15146 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
15147 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
15148 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u575xx.h16652 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
16653 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
16655 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
16656 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
16657 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u585xx.h17259 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
17260 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
17262 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
17263 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
17264 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u595xx.h17737 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
17738 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
17740 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
17741 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
17742 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5a5xx.h18344 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
18345 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
18347 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
18348 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
18349 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5f7xx.h19327 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
19328 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
19330 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
19331 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
19332 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u599xx.h21505 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
21506 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
21508 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
21509 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
21510 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5g7xx.h19934 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
19935 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
19937 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
19938 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
19939 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5f9xx.h22465 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
22466 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
22468 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
22469 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
22470 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5a9xx.h22112 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
22113 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
22115 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
22116 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
22117 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…
Dstm32u5g9xx.h23072 #define RCC_CCIPR2_SAI1SEL_Pos (5U) macro
23073 #define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E…
23075 #define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000002…
23076 #define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000004…
23077 #define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x0000008…