Searched refs:RCC_CCIPR2_I2C5SEL_0 (Results 1 – 10 of 10) sorted by relevance
679 #define RCC_I2C5CLKSOURCE_SYSCLK RCC_CCIPR2_I2C5SEL_0681 #define RCC_I2C5CLKSOURCE_MSIK (RCC_CCIPR2_I2C5SEL_1 | RCC_CCIPR2_I2C5SEL_0)
549 … (RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */
17775 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
18385 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
19368 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
21549 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
19978 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
22509 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
22159 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro
23119 #define RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) /*!< 0x0100000… macro