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Searched refs:RCC_CCIPR1_USART2SEL_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h467 #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos …
468 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC…
469 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC…
470 … ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_…
798 #define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos <…
799 … (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h564 …E_PCLK1 LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x000000…
565 …E_PLL2Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIP…
567 …E_PLL3Q LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIP…
569 …E_HSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIP…
570 …E_CSI LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIP…
571 …E_LSE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, RCC_CCIP…
995 …URCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_USART2SEL, RCC_CCIPR1_USART2SEL_Pos, 0x000000…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h9201 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
9202 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
9204 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
9205 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
9206 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
Dstm32h523xx.h13628 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
13629 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
13631 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
13632 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
13633 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
Dstm32h562xx.h14518 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
14519 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
14521 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
14522 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
14523 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
Dstm32h533xx.h14177 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
14178 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
14180 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
14181 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
14182 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
Dstm32h573xx.h17160 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
17161 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
17163 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
17164 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
17165 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
Dstm32h563xx.h16611 #define RCC_CCIPR1_USART2SEL_Pos (3U) macro
16612 #define RCC_CCIPR1_USART2SEL_Msk (0x7UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000038…
16614 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
16615 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000010…
16616 #define RCC_CCIPR1_USART2SEL_2 (0x4UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000020…
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba52xx.h10280 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
10281 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C…
10283 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004…
10284 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
Dstm32wba54xx.h10588 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
10589 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C…
10591 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004…
10592 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
Dstm32wba5mxx.h10606 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
10607 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C…
10609 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004…
10610 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
Dstm32wba55xx.h10606 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
10607 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C…
10609 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004…
10610 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008…
/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h12062 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
12063 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x0000000C */
12065 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000004 */
12066 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000008 */
Dstm32l562xx.h12792 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
12793 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x0000000C */
12795 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000004 */
12796 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos)/*!< 0x00000008 */
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u575xx.h16573 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
16574 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
16576 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
16577 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u585xx.h17180 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
17181 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
17183 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
17184 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u595xx.h17658 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
17659 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
17661 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
17662 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5a5xx.h18265 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
18266 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
18268 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
18269 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5f7xx.h19248 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
19249 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
19251 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
19252 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u599xx.h21426 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
21427 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
21429 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
21430 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5g7xx.h19855 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
19856 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
19858 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
19859 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5f9xx.h22386 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
22387 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22389 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22390 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5a9xx.h22033 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
22034 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22036 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22037 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
Dstm32u5g9xx.h22993 #define RCC_CCIPR1_USART2SEL_Pos (2U) macro
22994 #define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22996 #define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…
22997 #define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000…